• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.664-665
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• 2013

본 논문에서는 멀티미디어프로세서 구성의 한가지 방법을 제안하였다. 제안한 멀티미디어프로세서는 각각의 문자, 소리, 비디오를 한 개의 칩안에서 다룰 수 있으며, 멀티미디어의 특징인 인터렉티브의 기능을 갖고 있다. 특히 제안한 멀티미디어프로세서는 소프트웨어 없이도 메모리매상의 어드레싱이 가능하다. 제아난 멀티미디어프로세서는 가상현실에 적용이 가능하다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1177-1180
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• 2005

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2755-2757
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• 2002

In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제16권1호
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• pp.17-22
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• 2010

소형 USB 저장장치에서부터 대용량 데이터베이스 서버에 이르기까지 플래시 메모리의 활용범위가 더욱 확장되어 감에 따라 저장된 데이터의 호환성은 플래시 메모리 관리 소프트웨어의 중요한 고려사항이다. 이를 위해 FTL(Flash Translation Layer)과 FAT 파일시스템이 플래시 메모리 관리를 위한 사실상 표준 소프트웨어로써 사용되고 있다. 그러나 동일한 FTL과 FAT 파일시스템을 다양한 하드웨어로 구성된 시스템에서 구동하는 경우 각각의 요구조건을 만족할 수 없는 문제가 발생한다. 따라서 본 논문에서는 재구성 가능하며 FAT 표준 데이터의 호환성 및 향상된 기능을 제공하는 통합 플래시 메모리 관리 소프트웨어인 INFLAWARE(INtegrated FLAsh softWARE)를 제안한다. 제안된 기법은 실제 플래시 메모리가 장착된 시스템에 구현되었으며, 실험을 통해 본 논문에서 제안한 기법이 기존 기법 대비 최대 27%, 평균 19%의 메모리 사용량 감소 효과를 가져 올 수 있으며 또한 map_destroy 기법의 적용을 통해 최대 21%, 평균 10%의 성능 향상이 있음을 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.719-722
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• 2005

The synthesis of the 3D images is the most important part of the virtual reality. The photon mapping is the best method for reality in the 3D graphics. This paper presents an architecture for photon mapping applications on SOC devices. The proposed architecture reduces the computation time to photonmap search and radiance estimation. Also this architecture is implemented by a SIMD processor which trades parallelism for frequency of operation.

• 한국IT서비스학회지
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• 제4권1호
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• pp.117-128
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• 2005

When we conduct development of a large-size SI project, it is highly necessary to utilize an appropriate application framework which helps to build a qualified software with high productivity in a short period of time. In this paper, we propose the architecture of a dynamically reconfigurable CBD application integration framework that has been used for developing large-scale e-business applications to achieve high development productivity and maintainability. This Integration framework can easily extend its functionalities, and dynamically change its configuration during run time according to the business category, such as applying interaction patterns among main components in software architecture, rules, policies, and environmental parameters. Dynamic reconfiguration has the feature to make applications be easily customized for changeable requirements. Through our application integration framework, huge sizes of contents can be managed according to the business category as well, by keeping configuration informations and huge volumes of source codes. In order to evaluate out application integration framework in terms of performance criteria, we present experimental results of throughputs from the framework by yielding dynamic configuration without any performance degradation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.153-155
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• 2009

Cleaning robot system consists of four parts; navigation system for moving of robot, cleaning system, power system, and main system with cleaning algorithm. Navigation system is the most expensive part because it has motors and sensors which is high price. Navigation system is also essential to service robot system, but user should buy two systems which are service robot system and cleaning robot system. If it is possible to share navigation system, user can save money. In this paper, we design the cleaning robot system based on modular architecture.

• 항공우주기술
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• 제12권2호
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• pp.131-139
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• 2013

본 논문은 소프트 CPU 기반의 소형 전장품 설계 및 개발에 대한 것을 다루고 있다. 소프트 CPU는 소프트웨어를 이용한 로직 합성을 통해서 FPGA 내부에 구성되는 마이크로 프로세서이다. 소형 전장품 개발을 위해 소프트 CPU중 Nios-II 프로세서를 적용하여 다양하고, 다시 구성할구 있고, 다시 조립 가능한 하부 모듈로 설계하고 개발하였다. 모듈 구조로 구성하기 위해서 메인 보드와 하부 보드 모두 전원과 데이터 버스가 공통으로 사용할 수 있도록 구성하였고, 선택적으로 사용할 수 있도록 하였다.

• 전기학회논문지
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• 제57권9호
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(4)
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• pp.123-126
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• 2001

Block filter implementation technique for uniform filter banks is uniform in this paper. By applying block filter into decimation and interpolation filters, it is shown that down and up samplers are cancelled out in respective liters. Furthermore by applying block filters into uniform filter banks, significant reduction for computational complexity is achieved since prototype filter can be shared in each channel implementation. Also, it is shown that proposed implementation is a reconfigurable structure in terms of order variation.