• Title/Summary/Keyword: receiver design

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Thermal Performance of Air receiver with a Change of Flow direction for Dish Solar Collector (공기식 흡수기의 유동 방향에 따른 $5kW_t$급 접시형 태양열 집열기의 열성능 분석)

  • Seo, Joo-Hyun;Kang, Kyung-Moon;Lee, Ju-Han;Oh, Sang-June;Seo, Tae-Beom
    • 한국신재생에너지학회:학술대회논문집
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    • 2008.05a
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    • pp.182-185
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    • 2008
  • The thermal performance of air receiver with a change of flow direction for dish solar collector. This system is installed and operated in Incheon, Korea. The thermal capacity of the system is about 5 kW thermal. The aperture diameter of the cylindrical-shape receiver which is made of stainless steel is 100 mm, and the height is 210 mm. Experiments are being carried out to investigate the thermal performance variation of the receivers with several design parameters such as the shape of the receiver, the flow directions and the flow rate of air. First, air flows into the upper part of the receiver, which is the opposite side of the aperture. After the air flows through the inside receiver, that goes out of the receiver through 3 exits which are located near the aperture. Second, air flows into the backside of the receiver, Which is the forward side of the aperture. After the air flows through the inside receiver, that goes out of the receiver through 1 exit. The results show that the system efficiency and receiver efficiency increase as the volume flow rate increases as expected.

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System Design Considerations for a ZigBee RF Receiver with regard to Coexistence with Wireless Devices in the2.4GHz ISM-band

  • Seo, Hae-Moon;Park, Yong-Kuk;Park, Woo-Chool;Kim, Dong-Su;Lee, Myung-Soo;Kim, Hyeong-Seok;Choi, Pyung
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.2 no.1
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    • pp.37-49
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    • 2008
  • At the present time the task of designing a highly integrated ZigBee radio frequency (RF) receiver with an excellent coexistence performance is still very demanding and challenging. This paper presents a number of system issues and design considerations for a ZigBee RF receiver, namely IEEE 802.15.4, for coexistence with wireless devices in the 2.4-GHz ISM-band. With regard to IEEE 802.15.4, the paper analyzes receiver performance requirements for; system noise figure (NF), system third-order intercept point (system-IIP3), local oscillator phase noise and selectivity. Based on some assumptions, the paper illustrates the relationship between minimum detectable signal (MDS) and various situations that involve the effects of electromagnetic interference generated by other wireless devices. We infer the necessity of much more stringent specification requirements than the published standard for various wireless communication field environments

ADC-Based Backplane Receivers: Motivations, Issues and Future

  • Chung, Hayun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.3
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    • pp.300-311
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    • 2016
  • The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

Study on the Basic Design of Large Scale Solar Thermal Power Plant System (대규모 태양열 발전시스템 기본설계 특성 분석)

  • Kim, Jong-Kyu;Kang, Yong-Heack;Kim, Jin-Su;Lee, Sang-Nam;Yu, Chang-Kyun;Yun, Hwan-Ki
    • 한국신재생에너지학회:학술대회논문집
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    • 2006.06a
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    • pp.576-579
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    • 2006
  • This paper describes characteristics and procedure of the basic design of large scale solar thermal power plant system. The evaluation is based on the operating data of CESA-I, solar central receiver plant. In order to evaluate the solar irradiation on the receiver, it is necessary to calculate the amount of thermal energy consumption at steam turbine and storage system in the STPPS. Especially, it is need to take into account of the storage and operating time to design a plant efficiently. In addition, basic design is performed for the CESA-I using the software tool of THERMOFLEX program. Based on the results, It is at lowed to use the program to investigate detail performance of each units of the STPPS by varying the operating conditions.

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A FPGA Implementation of a Rotary Machine Receiver with Detecting a Header on the Asynchronous Serial Communication System (비동기 방식의 직렬통신 시스템에서 헤드 검출 기능을 가진 회전기용 리시버의 FPGA 구현)

  • Kang, Bong-Soon;Lee, Chang-Hoon;Kim, In-Kyu;Ha, Ju-Young;Kim, Ju-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.1
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    • pp.88-94
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    • 2005
  • This paper presents the design and implementation of a receiver operating between a rotary machine encoder and DSP. The receiver connects with the encoder using 1 bit serial data and DSP using 16 bits bus line. The receiver and encoder use the different operating frequency each other. We suggest a new apparatus and method of synchronized code for header detection in 1bit serial communication. The system operating frequency can be changed into 20MHz or 60MHz by using the external port such as 'clk_select'.

A study on the RF receiving system design and on the performance improvement for PCS mobile station (개인휴대통신을 위한 이동국 RF 수신시스템의 설계 및 성능개선에 관한 연구)

  • 오정일;천종훈
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.11
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    • pp.66-75
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    • 1997
  • We derive the system design parameters to implement the receiving system for the PCS mobile station to satisfy the J-sTD-018 which is the PCS mobile station(MS) minimum performance. Also we analyze the system performance and intermodulation spurious due to the values of a device cause the system performance degradation, is proposed. The simulation shows the receiver's maximum system noise figure to satisfy the receiver selectivity is approximately 11 dB. While the MS noise figure is 10dB with system margin 1 dB, the minimum selectivity is -71 dB at 1.25MHz frequency offset from the carrier frequency. And the input 3rd order intercept point of the MS class I and the MS class II~V is -9.5 dBm and -14dBm respectively. When the interference power level at the receiver is small, the receiver has better performance as we increase the gain of the LNA. However, when the interference level at the receiver is large, the receiver performance is heavily affected by the spurious as we increase the gain of the LNA. Thus, we proved the effectiveness of the LNA On/Off switching technique as to reduce the effect of the spurious.

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FPGA Implementation of a BFSK Receiver for Space Communication Using CORDIC Algorithm (CORDIC 알고리즘을 이용한 우주 통신용 BFSK 수신기의 FPGA 구현)

  • Ha, Jeong-Woo;Lee, Mi-Jin;Hur, Yong-Won;Yoon, Mi-Kyung;Byon, Kun-Sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.06a
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    • pp.179-183
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    • 2007
  • This paper is to implement a low power frequency Shift Keying(FSK) receiver using Xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

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Design and Applications of a Generalized Software-Based GNSS IF Signal Generator

  • Lim, Deok-Won;Park, Chan-Sik;Lee, Sang-Jeong
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.211-215
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    • 2006
  • In this paper, design and applications of a generalized, versatile and customizable IF signal generator that can model the modernized GPS and Galileo signal is given. It generates IF sampled data that can be directly used by a software receiver. Entire constellation of satellites which is independent of satellite-user geometry is easily determined using a real or simulated ephemeris data. Since the IF center frequency, sampling frequency and quantization bit number are user location dependent parameters, their effects are also considered in IF signal generator. The generalized IF signal generator will be very well suited for the development phase of a software receiver due to its versatility. The full access to the sampling frequency, front-end filter definition and ADC parameters also offers a great opportunity for cost-effective analysis of tracking loops and error mitigation techniques at the receiver level. Interference sources can be easily added to the generator to simulate specific environments. This software IF signal generator can also be used to feed a multi-frequency multi-system software receiver for the prototyping of a combined GPS/Galileo receiver. The test result using the generated signals and a real software receiver shows the effectiveness of the implemented IF signal generator.

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The Hardware Design for GPS Data Acquisition Circuit (GPS 데이타 수신을 위한 하드웨어 설계)

  • 정영태;김민호;김명돈;홍성일;변건식;정만영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.10
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    • pp.8-17
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    • 1995
  • Recently, in a variety of the application fields, it is interested in GPS receiver as the use of GPS(Global Positioning System) is increased. In this paer, we propose that a type of new receiver of a simple structure as GPS data receiver. This proposed receiver consists of RF stage, local C/A(Coarse/Acquisition) code generator, C/A code correlator, data demodulator and microprocessor controller as a GPS single channel data receiver using the L1 carrier . It is confirmed that the proposed receiver operates well as GPS raw data receiver through experiment.

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DESIGN OF THE IF DISTRIBUTOR AND V/F CONVERTER FOR RECEIVER SYSTEM (우주전파 수신기를 위한 IF 분배기 및 V/F 컨버터 설계)

  • Kim, Kwang-Dong;Yim, In-Sung;Byun, Do-Young;Song, Min-Gyu
    • Publications of The Korean Astronomical Society
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    • v.22 no.3
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    • pp.83-87
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    • 2007
  • We designed the Intermediate Frequency(IF) distributor for multi beam backend system and manufactured Voltage to Frequency Converter(VFC) to measure the multi-beam receiver performance. Multi beam receiver has 15 channel receivers and can get 15 spectrums at once. The multi beam receiver has more observation efficiency than single beam receiver. We manufactured the 15 IF distributors to distribute IF signal for Autocorrelation spectrometer that is radio signal processor. Also, we manufactured the VF Converter to test the performance measurement of receiver for Korea VLBI Network(KVN) system which is under-construct in Seoul, Ulsan and Jeju. As a result of performance measurement, we could obtain linearity of 99.4% on the input power vs output frequency and measured the operating range of input frequency.