• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.19-26
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• 2009

Recently, the Main Memory DBMS is gradually being expanded by the appearance of a large capacity of a Main Memory System, the increase in business area where it requires a real time process, and the rise of the users' required level. The Main Memory DBMS, which is able to go through a large capacity data process of the disk-based DBMS and guarantees a high efficiency, has domestically developed and has been put to a practical use. This paper presents an examination of the applied technologies and the limits of Altibase system, which is Main Memory DBMS. Moreover, it evaluated and performed a comparative analysis on the performance level of the Main Memory DBMS and the disk-based DBMS based on the same application. After five trials of the experiment based on the operating application, it was confirmed that the performance level of the Main Memory DBMS is enhanced and is higher by 4.13 to 7.89 times than the disk-based DBMS.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.3
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• pp.13-19
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• 2016

Spark, an in-memory big-data processing framework is popular to use for real-time processing workload. Spark can store all intermediate data in the cluster memory so that Spark can minimize I/O access. However, when the resident memory of workload is larger that the physical memory amount of the cluster, the total performance can drop dramatically. In this paper, we analyse the factors of bottleneck on PageRank Application that needs many memory through experiment, and cluster the Spark with Tachyon File System for using memory to solve the factor of bottleneck and then we improve the performance about 18%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.1
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• pp.87-96
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• 2006

In this paper, we examine general digital evidence collection process which is according to RFC3227 document[l], and establish specific steps for memory information collection. Besides, we include memory dump process to existing digital evidence collection process, and examine privacy information through dumping real user's memory and collecting pagefile which is part of virtual memory system. Especially, we discovered sensitive data which is like password and userID that exist in the half of pagefiles. Moreover, we suggest each analysis technique and computer forensic process for memory information and virtual memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.349-354
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• 2009

In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.107-116
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• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.

• ETRI Journal
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• v.43 no.1
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• pp.141-151
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• 2021

Several methods exist for detecting hacking programs operating within online games. However, a significant amount of computational power is required to detect the illegal access of a hacking program in game clients. In this study, we propose a novel detection method that analyzes the protected memory area and the hacking program's process in real time. Our proposed method is composed of a three-step process: the collection of information from each PC, separation of the collected information according to OS and version, and analysis of the separated memory information. As a result, we successfully detect malicious injected dynamic link libraries in the normal memory space.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.17-25
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• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.7
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• pp.2513-2530
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• 2021

With the fast development of information and communication technologies, video streaming services and applications are increasing rapidly. However, the network condition is volatile. In order to provide users with better quality of service, it is necessary to develop an accurate and low-complexity model for Quality of Experience (QoE) prediction of time-varying video. Memory effects refer to the psychological influence factor of historical experience, which can be taken into account to improve the accuracy of QoE evaluation. In this paper, we design subjective experiments to explore the impact of Short-Term Memory (STM) on QoE. The experimental results show that the user's real-time QoE is influenced by the duration of previous viewing experience and the expectations generated by STM. Furthermore, we propose analytical models to determine the relationship between intrinsic video quality, expectation and real-time QoE. The proposed models have better performance for real-time QoE prediction when the video is transmitted in a fluctuate network. The models are capable of providing more accurate guidance for improving the quality of video streaming services.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.319-330
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• 2001

In virtual memory system, when a process attempts to access a page that is not resident in memory, the system generates and handles a page fault that causes unpredictable delay. So virtual memory system is not appropriate for the real-time system, because it can increase the deadline miss ratio of real-time task. In multimedia system, virtual memory system may degrade the QoS(quality of service) of multimedia application. Furthermore, in general-purpose operating system, whenever a new task is dynamically loaded, virtual memory system suffers from extensive page fault that cause transient overloading state. In this paper, we present efficient overloading control mechanism called RBPFH (Rate-Based Page Fault Handling). A significant feature of the RBPFH algorithm is page fault dispersion that keeps page fault ratio from exceeding available bound by monitoring current system resources. Furthermore, whenever the amount of available system resource is changed, the RBPFH algorithm dynamically adjusts the page fault handling rate. The RBPFH algorithm is implemented in the Linux operating system and its performance measured. The results demonstrate RBPFH\`s superior performance in supporting multimedia applications. Experiment result shows that RBPFH could achieve 10%∼20% reduction in deadline miss ratio and 50%∼60% reduction in average delay.