• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.334-337
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• 2005

This paper describes the implementation of DCS communication network that provides high bandwidth and reliability. The network for DCS in this paper adopts the Reflective Memory (RM) architecture and Fast Ethernet physical media that have 100Mbps bandwidth. Also, this network uses Ring Enhancement Device (RED) which was invented to reduce the time delay of each node. The DCS network that is introduced in this paper is named as ERCNet(Ethernet based Real-time Control Network). This paper describes the architecture and working algorithms of ERCNet and performs numerical analysis. In addition, the performance of ERCNet is evaluated by experiment using the developed ERCNet network.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.839-842
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• 1998

The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.17-21
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• 2004

본 논문에서는 실시간으로 상수 및 변수의 병렬 매칭이 가능한 새로운 구조의 하드웨어 기반 룰-베이스시스템 구조를 제안한다. 이 시스템은 context-aware computing 시스템에서 상황 인식을 위한 기법으로 적용될 수 있다. 제안된 구조는 기존의 하드웨어 기반의 구조가 가지는 룰의 표현 및 룰의 구성에서 발생하는 제약을 상당히 감소시킬 수 있다. 이를 위해 변형된 형태의 content addressable memory(CAM)와 crossbar switch network(CSN)가 사용되었다. 변형된 형태의 CAM으로 구성된 지식-베이스는 동적으로 데이터의 추가 및 삭제가 가능하다. 또한 CSN은 input buffer와 working memory(WM) 사이에 위치하여, 시스템 외부 및 내부에서 동적으로 생성되거나, 시스템 설정에 의해 지정된 데이터들의 조합 및 pre-processing module(PPM)을 이용한 연산을 통하여 WM을 구성하는 데이터를 생성시킨다. 이 하드웨어 룰-베이스 시스템은 SystemC 2.0을 이용하여 설계하였으며 시뮬레이션을 통하여 그 동작을 검증하였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.403-404
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• 2008

In this paper, a new 4-way search window is developed for H.264 Motion Estimation(ME) to improve the memory bandwidth. The proposed 4-way(up, down, left, right) search window could improve the reuse of overlapped window data to reduce the redundancy access factor by 1.4, though the 1/3-way search window requires $7.7{\sim}11$ times of data retrieval redundantly. In experiments, the new implementation of 4-way search window on Altera Stratix-III could deal with CIF ($352{\times}288$) video of 3 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps real time at 55.2MHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.163-170
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• 2003

The optimal Bayesian filter for a single target is known to provide the best tracking performance in a cluttered environment. However, its main drawback is the increase in memory size and computation quantity over time. In this paper, the inevitable predicament of the optimal Bayesian filter is resolved in a suboptimal fashion through the use of a receding horizon strategy. As a result, the problems of memory and computational requirements are diminished. As a priori information, the horizon initial state is estimated from the validated measurements on the receding horizon. Consequently, the suboptimal algorithm proposed allows for real time implementation.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.863-866
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• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• ETRI Journal
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• v.38 no.3
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• pp.425-434
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• 2016

A novel average magnitude difference function (AMDF)-based pitch detection scheme (PDS) is proposed to achieve better performance in speech quality. A performance evaluation of the proposed PDS is carried out through both a simulation and a real-time implementation of a speech analysis-synthesis system. The parameters used to compare the performance of the proposed PDS with that of PDSs that are based on either a cepstrum, an autocorrelation function (ACF), an AMDF, or circular AMDF (CAMDF) methods are as follows: percentage gross pitch error (%GPE); a subjective listening test; an objective speech quality assessment; a speech intelligibility test; a synthesized speech waveform; computation time; and memory consumption. The proposed PDS results in lower %GPE and better synthesized speech quality and intelligibility for different speech signals as compared to the cepstrum-, ACF-, AMDF-, and CAMDF-based PDSs. The computational time of the proposed PDS is also less than that for the cepstrum-, ACF-, and CAMDF-based PDSs. Moreover, the total memory consumed by the proposed PDS is less than that for the ACF- and cepstrum-based PDSs.

• The KIPS Transactions:PartD
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• v.17D no.5
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• pp.353-358
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• 2010

Unlike the traditional databases, queries on XML streams are restricted to a real time processing and memory usage. In this paper, a robust labeling scheme is proposed, which quickly identifies structural relationship between XML fragments. The proposed labeling scheme provides an effective query processing by removing many redundant operations and minimizing the number of fragments being processed. In experimental results, the proposed labeling scheme efficiently processes query processing and optimizes memory usage.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.346-348
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• 2006

실시간 운영체제를 탑재한 임베디드 시스템(Embedded System)은 특성상 다른 시스템에 비해 상대적으로 저 용량의 메모리를 지닌다. 따라서 제한된 메모리를 효율적으로 사용할 수 있는 기법이 적용될 필요가 있다. 외부 단편화(External Fragmentation)로 생긴 메모리 공간을 재조정하는 기법도 효율적인 메모리 사용을 위한 방안이며, 본 논문에서는 실시간 운영체제에서 가용한 메모리를 효율적으로 활용할 수 있는 메모리 압축(Memory Compaction) 기법에 대해서 설계 및 구현하였다.