• Journal of KIISE:Databases
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• v.29 no.6
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• pp.464-476
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• 2002

Main-memory database systems which reside entire databases in main memory are suitable for high-performance real-time transaction processing. If two-phase locking(2PL) as concurrency control protocol is used for the transactions accessing main-memory databases, however, the possibility of lock conflict will be low but lock operations become relatively big overhead in total transaction processing time. In this paper, We designed a real-time static locking(RT-SL) protocol which minimizes lock operation overhead and reflects the priority of transactions and we implemented it on a main-memory real-time database system, Mr.RT. We also evaluate and compare its performance with the existing real-time locking protocols based on 2PL such as 2PL-PI and 2PL-HP. The extensive experiments reveal that our RT-SL outperforms the existing ones in most cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.150-155
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• 2008

This paper is related to developing new Bit Error Rate (BER) simulator, Sam sung BER simulator (SBERS), in order to evaluate the link compliance and all kinds of effects of link compliance in a real environment. SBERS allows to generate transmit pulse accurately by using the various parameters, and obtain the eye diagram and bathtub curve, which represents the performance of link, by calculating the transmit pulse and the measured frequency response characteristics. SBERS give results as same as real environment after taking account of distribution and value of noise. To verify the accuracy of simulator, we derive the simulated and measured result and compare eye opening. The difference came out to be within 5% error. It is possible to estimate the real environment and design the transmitter and receiver circuit effectively using new BER simulator, SBERS.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.36-45
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• 2002

This paper introduces the design and implementation of a flash memory simulator to emulate a real flash memory. Since this simulator provides exact execution time information and parameter testing functions as well as the type, total capacity, block size, and page size of flash memory, it can be used as a real flash memory as viewed by the operating system. Furthermore, the simulator provides time logging functions of the internal routines of the flash memory management software allowing the monitoring of bottlenecks within the software. Finally, we show the performance measurements of applications under the Linux operating systems on both the simulator and a test board verifying the simulator's use as a replacement for real flash memory.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.105-108
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• 2001

This paper proposed an efficient memory scheduling method (E$^2$M$^2$) by which the real-time image compression using 2-dimensional discrete wavelet transform(2-D DWT) is possible in an FPGA chip. In this paper, we assumed that the 2-D DWT was performed as the Mallat-tree. After the memory mapping method was proved in software, the memory controller was designed for an commercial SDRAM IC.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.189-200
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• 2001

This paper proposes a memory allocation model for Real-Time Linux. The proposed model allows users to create several continuous memory regions in an application, to specify an appropriate region allocation policy for each memory region, and to request memory blocks from a necessary memory region. Instead of using single memory management module in order to support the proposed model, we adopt two-layered structure that is consisted of region allocators implementing allocation policies and a region manager controlling regions and region allocator modules. This structure separates allocation policy from allocation mechanism, thus allows system developers to implement same allocation policy using different algorithms in case of need. IN addition, it enables them to implement new allocation policy using different algorithms in case of need. In addition, it enables them to implement new allocation policy easily as long as they preserver predefined internal interfaces, to add the implemented policy into the system, and to remove unnecessary allocation policies from the system, Because the proposed model provides various allocation policies implemented previously, system builders can also reconfigure the system by just selecting most appropriate policies for a specific application without implementing these policies from scratch.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.43-48
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• 2022

Recently, due to the rapid performance improvement of smartphones and the increase in background executions of mobile apps, multitasking has become common on mobile platforms. Unlike traditional desktop and server apps, response time is important in most mobile apps as they are interactive tasks, and some apps are classified as real-time tasks with deadlines. In this paper, we discuss how to meet the requirements of heterogeneous multitasking in managing memory of real-time and interactive tasks when they are executed together on a smartphone. To do so, we analyze the memory requirement of real-time tasks, and propose a model that has the ability of allocating memory to multitasking tasks on a smartphone. Trace-driven simulations with real-world storage access traces captured by heterogeneous apps show that the proposed model provides reasonable performance for interactive tasks while guaranteeing the requirement of real-time tasks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.436-439
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• 2011

As mobile digital devices have come into more widespread use, the demand for mobile storage devices have been increasing rapidly and most of digital cameras and camcorders are using SD memory cards. The SD memory card are generally employing a form of copying data into a personal computer after storing user data based on flash memory. The current paper proposes the SD memory card of being capable of storing photograph and image data through network rather than using a method of storing data in flash memory. By delivering data and memory address values obtained through SD Slave IP to network server without sending them to flash memory, one can store data necessary to be stored in a computer's SD memory in real time in a safe and convenient way.

• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1705-1708
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• 2005

Recently, flash memory is becoming popular as storage system to store and retrieve multimedia files. However, there are few researches about multimedia file system for flash memory based storage devices. We have been designing and developing a novel multimedia file systems for flash memory. In this paper, we describe the semantics of real-time retrieval of multimedia data and present scheduling scheme to guarantee the real-time requirements in our multimedia file system.

• International journal of advanced smart convergence
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• v.1 no.2
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• pp.26-29
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• 2012

Recently, to efficiently support the real-time requirements of RTLS( Real Time Location System) services, interest in the main memory DBMS is rising. In the main memory DBMS, because all data can be lost when the system failure happens, the recovery method is very important for the stability of the database. Especially, disk I/O in executing the log and the checkpoint becomes the bottleneck of letting down the total system performance. Therefore, it is urgently necessary to research about the recovery method to reduce disk I/O in the main memory DBMS. Therefore, In this paper, we analyzed existing log techniques and check point techniques and existing main memory DBMSs' recovery techniques for recovery techniques research for main memory DBMS.