BER Simulator Development for Link Compliance Analysis |
Kang, Hyun-Chul
(Memory Division, Samsung Electronics Co., Ltd)
Kim, Woo-Seop (Memory Division, Samsung Electronics Co., Ltd) Lee, Jae-Wook (Memory Division, Samsung Electronics Co., Ltd) Jang, Young-Chan (Memory Division, Samsung Electronics Co., Ltd) Park, Hwan-Wook (Memory Division, Samsung Electronics Co., Ltd) Kim, Jong-Hoon (Memory Division, Samsung Electronics Co., Ltd) Lee, Jung-Bae (Memory Division, Samsung Electronics Co., Ltd) Kim, Chang-Hyun (Memory Division, Samsung Electronics Co., Ltd) |
1 | "Measuring Jitter in Digital Systems", Application Note 1448-1, Agilent Technology |
2 | Bryan K. Casper, Matthew Haycock, Randy Mooney, "An Accurate and Efficient Analysis Method for Multi-Gb/s Chip-to-chip Signaling Schemes," Symposium On VLSI Circuit Digest of Technical Papers, 2002 |
3 | http://www.stateye.org |
4 | A. Sanders, M. Resso, J. D/Ambrosia, "Channel Compliance Testing Utilizing Novel Statistical Eye Methodology," DesignCon 2004 |
5 | "Jitter Analysis : The dual-Dirac Model, RJ/DJ, and Q-Scale", White Paper, Agilent Technology |
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