• Journal of the Korean institute of surface engineering
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• v.36 no.2
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• pp.161-167
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• 2003

In order to investigate the effects of pulse plating conditions on the electrodeposition of trivalent chromium, electroplating experiments from bath with low concentration of trivalent chromium were performed. The variation of current efficiency of chromium electroplating with the electroplating conditions was explained. The maximum current efficiency of pulse plating is 6.4 times as high as that of direct plating at the same mean current density The nodular size increased with pulse plating time and the pulse frequency.

• Korean Journal of Materials Research
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• v.11 no.9
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• pp.802-809
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• 2001

Electroplating is an attractive alternative deposition method for copper with the need for a conformal and conductive seed layer In addition, the Cu seed layer should be highly pure so as not to compromise the effective resistivity of the filled copper interconnect structure. This seed layer requires low electrical resistivity, low levels of impurities, smooth interface, good adhesion to the barrier metal and low thickness concurrent with coherence for ensuring void-free fill. The electrical conductivity of the surface plays an important role in formation of initial Cu nuclei, Cu nucleation is much easier on the substrate with higher electrical conductivities. It is also known that the nucleation processes of Cu are very sensitive to surface condition. In this study, copper seed layers deposited by magnetron sputtering onto a tantalum nitride barrier layer were used for electroplating copper in the forward pulsed mode. Prior to electroplating a copper film, the Cu seed layer was cleaned by plasma H$_2$ and $N_2$. In the plasma treatment exposure tome was varied from 1 to 20 min and plasma power from 20 to 140W. Effects of plasma pretreatment to Cu seed/Tantalum nitride (TaN)/borophosphosilicate glass (BPSG) samples on electroplating of copper (Cu) films were investigated.

• Journal of the Semiconductor & Display Technology
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• v.14 no.1
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• pp.67-71
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• 2015

Pulse electroplating was studied to form nanocrystal structure effectively by changing plating current density and duty cycle. When both of plating current density and duty cycle were decreased from $100mA/cm^2$ and 70% to $50mA/cm^2$ and 30%, the P content in the Ni matrix was increased almost up to the composition of $Ni_3P$ compound and the grain growth after annealing was retarded as well. The as-plated hardness values ranging from 660 to 753 HV are mainly based on the formation of nanocrystal structure. On the other hand, the post-anneal hardness values ranging from 898 to 1045 HV, which are comparable to the hardness of hard Cr, are coming from how competition worked between the precipitation of $Ni_3P$ and the grain coarsening. According to the ANOVA and regression analysis, the plating current density showed more strong effect on nanocrystal size and film hardness than the duty cycle.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.685-688
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• 2000

Pulse plating is about to deposit material at high current density compared to conventional DC plating. For example pulse plating can get more fine grain can improve adhension and metal distribution and current efficiency can reduce internal stress and crack. therefore we studied pulsed power supply which has high current density and improve deposition quality and increase plating speed in this paper.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.77-81
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• 2017

Pulse electroplating of Ni-P alloy was studied to fulfill the material requirement to the advanced vertical probe tip in wafer probe card. The major concerns are for the electrical conductivity and yield strength. Plating parameters such as current density, duty cycle and solution components were examined to obtain the nanocrystal structure and proper percentage of phosphorus, leading to how to control the nanocrystal grain growth and precipitation of $Ni_3P$ after heat treatment. Among the parameters, the amount of phosphorus acid was the main factor affecting on the grain size and sheet resistance, and the amount of 0.1 gram was appropriate. Since hardness in Ni-P alloy is increased by as-plated nanocrystal structure plus precipitation of $Ni_3P$, the concentration of P less than 15 at% was better choice for the grain coarsening without minus in hardness value. The following heat treatment made grain growth and dispersion of precipitates adjustable to meet the target limit of resistance of $100m{\Omega}$ and hardness number of over 1000Hv. The Ni-P alloy will be a candidate for the substitute of the conventional probe tip material.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.123.1-123.1
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• 2017

Hybrid solar cells have intensively studied in recent years due to their advantages such as cost effectiveness and possibility of applications in flexible and transparent devices. It is critical to fabricate individual layer composed of organic and inorganic materials in the hybrid solar cell at low cost. Therefore, it is required to manufacture cheaply and enhance the photon-to-electricity conversion efficiency of each layer in the flexible solar cell industry. In this research, we fabricated pure Cu metal mesh electrode prepared by using electroplating and/or electroless plating on the Ni mold which was manufacture through photolithography, electroforming, and polishing process. Copper mesh was formed on the surface of nickel metal working master when pulsed electrolytic copper deposition were performed at various plating parameters such as plating time, current density, and so on. After electrodeposition at 2ASD for 5~30seconds, the line/pitch/thickness of copper mesh sheet was $1.8{\sim}2.0/298/0.5{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.