• 제목/요약/키워드: pseudorandom generator

검색결과 17건 처리시간 0.029초

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

  • Hwang, Soo-Yun;Park, Gi-Yoon;Kim, Dae-Ho;Jhang, Kyoung-Son
    • ETRI Journal
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    • 제32권2호
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    • pp.222-229
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    • 2010
  • A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

PRaCto: Pseudo Random bit generator for Cryptographic application

  • Raza, Saiyma Fatima;Satpute, Vishal R
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제12권12호
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    • pp.6161-6176
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    • 2018
  • Pseudorandom numbers are useful in cryptographic operations for using as nonce, initial vector, secret key, etc. Security of the cryptosystem relies on the secret key parameters, so a good pseudorandom number is needed. In this paper, we have proposed a new approach for generation of pseudorandom number. This method uses the three dimensional combinational puzzle Rubik Cube for generation of random numbers. The number of possible combinations of the cube approximates to 43 quintillion. The large possible combination of the cube increases the complexity of brute force attack on the generator. The generator uses cryptographic hash function. Chaotic map is being employed for increasing random behavior. The pseudorandom sequence generated can be used for cryptographic applications. The generated sequences are tested for randomness using NIST Statistical Test Suite and other testing methods. The result of the tests and analysis proves that the generated sequences are random.

땋임군에서의 안전성이 증명 가능한 유사난수 생성기 (A Provably secure Pseudorandom generator from Braid groups)

  • 이언경;한상근
    • 정보보호학회논문지
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    • 제11권3호
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    • pp.13-22
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    • 2001
  • 유사난수성(pseudorandomness)은 진정한 난수성(true randomness)을 대신하여 실제 상황에서 사용되는 개념으로서 현대 암호학의 중요한 한 분야이다. 본 논문은 땋임이론(braid theory)에서의 어려운 문제 중 하나인 공액문제(conjugacy problem)에 기반하여 단순하고 실용적인 유사난수 생성기(pseudorandom generator)를 설계한다. 그리고 그 생성기가 암호 학적으로 공액문제를 변형한 또 하나의 어려운 문제 만큼 안전함을 증명한다.

Golomb의 공리를 이용한 Shrinking Generator의 분석 (Cryptanalysis of Shrinking Generator by Golomb's Randomness Postillate)

  • 김정헌;권기호;박명진
    • 한국군사과학기술학회지
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    • 제4권2호
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    • pp.105-111
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    • 2001
  • The shrinking generator is simple and stateable, and known that has good security properties. The bits of one output( $R_1$) are used to determine whether the corresponding bits of the second output will be used as part of the overall keystream. Two LFSRs consisting the generator generate pseudorandom sequences satisfying Golomb's postulates. We used this property to analyze the stream of LFSR $R_1$ of the generator.

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An Improved Pseudorandom Sequence Generator and its Application to Image Encryption

  • Sinha, Keshav;Paul, Partha;Amritanjali, Amritanjali
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제16권4호
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    • pp.1307-1329
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    • 2022
  • This paper proposes an improved Pseudorandom Sequence Generator (PRSG) based on the concept of modular arithmetic systems with non-integral numbers. The generated random sequence use in various cryptographic applications due to its unpredictability. Here the mathematical model is designed to solve the problem of the non-uniform distribution of the sequences. In addition, PRSG has passed the standard statistical and empirical tests, which shows that the proposed generator has good statistical characteristics. Finally, image encryption has been performed based on the sort-index method and diffusion processing to obtain the encrypted image. After a thorough evaluation of encryption performance, there has been no direct association between the original and encrypted images. The results show that the proposed PRSG has good statistical characteristics and security performance in cryptographic applications.

A NEW VERSION OF FIRST RETURN TIME TEST OF PSEUDORANDOMNESS

  • Kim, Dong-Han
    • Journal of the Korean Society for Industrial and Applied Mathematics
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    • 제12권2호
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    • pp.109-118
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    • 2008
  • We present a new version of the first return time test for pseudorandomness. Let $R_n$ be the first return time of initial n-block with overlapping. An algorithm to calculate the probability distribution of the first return time $R_n$ for each starting block is presented and used to test pseudorandom number generators. The standard Z-test for log $R_n$ is applied to test the pseudorandom number generators.

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임베디드 시스템에 적합한 듀얼 모드 의사 난수 생성 확장 모듈의 설계 (Dual-mode Pseudorandom Number Generator Extension for Embedded System)

  • 이석한;허원;이용석
    • 대한전자공학회논문지SD
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    • 제46권8호
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    • pp.95-101
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    • 2009
  • 난수 생성 함수는 소프트웨어를 사용한 시뮬레이션 테스트나 통신 프로토콜 검증 등 수많은 어플리케이션에 사용되어진다. 이런 상황에서 난수의 randomness는 사용 어플리케이션에 따라서 다르게 필요할 수 있다. 반드시 randomness가 보장된 랜덤 함수를 통한 고품질의 난수를 생성해야 할 때가 있고, 단지 난수와 비슷한 형태를 가진, randomness가 보장되지 않은 난수가 필요할 때도 있다. 본 논문에서는 고속으로 동작하는 임베디드 시스템을 위한 듀얼 모드로 동작하는 하드웨어 난수 생성기를 제안하였다. 모드 1 에서는 높은 randomness를 가지는 난수를 6사이클마다 한 번씩 생성하게 되며, 모드 2 에서는 낮은 randomness를 가지는 난수를 매 사이클마다 생성할 수 있다. 테스트를 위해, ASIP(Application Specific Instruction set Processor)를 설계하였으며, 각 모드에 맞는 명령어 세트를 설계하였다. ASIP은 LISA언어를 사용하여, 5 stage MIPS architecture를 기반으로 설계되었고, CoWare 사의 Processor Generator를 통해서 HDL코드를 생성하였으며, HDL 모델은 동부 0.18um 공정으로 Synopsys사의 Design Compiler를 통해서 합성되었다. 설계되어진 ASIP으로 난수를 생성한 결과, 하드웨어 모듈을 추가하기 전에 비해 2.0%의 면적 증가 및 239%의 성능 향상을 보였다.

Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices

  • Cha, Jaewon;Kang, Sungho
    • ETRI Journal
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    • 제35권1호
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    • pp.166-169
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    • 2013
  • In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

최대길이 여원 CA 기반의 의사랜덤수열 분석 (Analysis of Pseudorandom Sequences Generated by Maximum Length Complemented Cellular Automata)

  • 최언숙;조성진
    • 한국전자통신학회논문지
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    • 제14권5호
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    • pp.1001-1008
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    • 2019
  • 고품질 의사랜덤수열 생성은 암호화 프로토콜을 포함한 많은 암호화 응용 프로그램에서 매우 중요한 부분이다. 그러므로 의사랜덤수열 생성기(Pseudo Random Number Generator, 이하 PRNG)는 암호시스템에서 키수열 생성하는데 꼭 필요한 요소이다. PRNG는 고품질의 랜덤한 큰 데이터 스트림을 효과적으로 생성해야 한다. CA 기반의 PRNG는 LFSR기반의 PRNG에 의해 출력되는 난수열보다 랜덤성이 우수하다는 사실은 이미 잘 알려져 있다. 본 논문에서는 비밀키 암호시스템에서 보다 안전한 비트스트림을 생성하고 키 공간을 확장할 수 있는 PRNG를 설계하기 위해 최대길이를 갖는 90/150 셀룰라 오토마타(Cellular Automata, CA)로부터 유도된 여원 CA가 최대길이 CA임을 보인다. 또한 90/150 최대길이 CA(MLCA)와 여원벡터로부터 유도된 여원 MLCA의 각 셀에서 출력되는 수열 중 비선형 수열을 출력하는 셀의 위치를 분석한다.

Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators

  • Barakat, Mohamed L.;Mansingka, Abhinav S.;Radwan, Ahmed G.;Salama, Khaled N.
    • ETRI Journal
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    • 제35권3호
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    • pp.448-458
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    • 2013
  • This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.