• ETRI Journal
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• v.32 no.2
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• pp.222-229
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• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.6161-6176
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• 2018

Pseudorandom numbers are useful in cryptographic operations for using as nonce, initial vector, secret key, etc. Security of the cryptosystem relies on the secret key parameters, so a good pseudorandom number is needed. In this paper, we have proposed a new approach for generation of pseudorandom number. This method uses the three dimensional combinational puzzle Rubik Cube for generation of random numbers. The number of possible combinations of the cube approximates to 43 quintillion. The large possible combination of the cube increases the complexity of brute force attack on the generator. The generator uses cryptographic hash function. Chaotic map is being employed for increasing random behavior. The pseudorandom sequence generated can be used for cryptographic applications. The generated sequences are tested for randomness using NIST Statistical Test Suite and other testing methods. The result of the tests and analysis proves that the generated sequences are random.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.13-22
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• 2001

The notion of pseudorandomness plays an important role in modem cryptography as well as computer science. We show a simple and practical construction of a pseudorandom generator based on the intractability of the problem in braid groups. The generator is proved as secure as a hard instance of a variant of the conjugacy problem.

• Journal of the Korea Institute of Military Science and Technology
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• v.4 no.2
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• pp.105-111
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• 2001

The shrinking generator is simple and stateable, and known that has good security properties. The bits of one output( $R_1$) are used to determine whether the corresponding bits of the second output will be used as part of the overall keystream. Two LFSRs consisting the generator generate pseudorandom sequences satisfying Golomb's postulates. We used this property to analyze the stream of LFSR $R_1$ of the generator.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.4
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• pp.1307-1329
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• 2022

This paper proposes an improved Pseudorandom Sequence Generator (PRSG) based on the concept of modular arithmetic systems with non-integral numbers. The generated random sequence use in various cryptographic applications due to its unpredictability. Here the mathematical model is designed to solve the problem of the non-uniform distribution of the sequences. In addition, PRSG has passed the standard statistical and empirical tests, which shows that the proposed generator has good statistical characteristics. Finally, image encryption has been performed based on the sort-index method and diffusion processing to obtain the encrypted image. After a thorough evaluation of encryption performance, there has been no direct association between the original and encrypted images. The results show that the proposed PRSG has good statistical characteristics and security performance in cryptographic applications.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.12 no.2
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• pp.109-118
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• 2008

We present a new version of the first return time test for pseudorandomness. Let $R_n$ be the first return time of initial n-block with overlapping. An algorithm to calculate the probability distribution of the first return time $R_n$ for each starting block is presented and used to test pseudorandom number generators. The standard Z-test for log $R_n$ is applied to test the pseudorandom number generators.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• ETRI Journal
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• v.35 no.1
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• pp.166-169
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• 2013

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.1001-1008
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• 2019

A high-quality pseudorandom sequence generation is an important part of many cryptographic applications, including encryption protocols. Therefore, a pseudorandom number generator (PRNG) is an essential element for generating key sequences in a cryptosystem. A PRNG must effectively generate a large, high-quality random data stream. It is well known that the bitstreams output by the CA-based PRNG are more random than the bitstreams output by the LFSR-based PRNG. In this paper, we prove that the complemented CA derived from 90/150 maximum length cellular automata(MLCA) is a MLCA to design a PRNG that can generate more secure bitstreams and extend the key space in a secret key cryptosystem. Also we give a method for calculating the cell positions outputting a nonlinear sequence with maximum period in complemented MLCA derived from a 90/150 MLCA and a complement vector.

• ETRI Journal
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• v.35 no.3
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• pp.448-458
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• 2013

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.