• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.4
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• pp.28-34
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• 2012

Installing surge protection devices for a low-voltage system is important to ensure the survival of electric or electronic devices and systems. If surge protection devices (SPD) are installed without consideration of the concept of lightning protection zones, the equipment to be protected might be damaged despite the correct energy coordination of SPDs. This damage is induced by the reflection phenomena on the cable connecting an external SPD and the load protected. These reflection phenomena depend on the characteristics of the output of the external SPD, the input of the loads, and the cables between the load and the external SPD. Therefore, the SPD has an effective protection distance under the condition of the specific load and the specific voltage protection level of SPD. In this paper, PSCAD/EMTDC software is used to simulate the residual voltage characteristics of SPD Entering the low-voltage device. And by applying a certain voltage level, the effective protection distances of SPD were analyzed according to the each load and length of connecting cable, and the effectiveness of SPD were verified.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.2
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• pp.29-35
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• 2013

For the purpose of designing and applying optimum surge protection, one of the essential points is to take into account the energy coordination between cascaded surge protective devices(SPDs) and it is important to obtain an acceptable sharing of the energy stress between two cascaded SPDs. In this paper, in case of two voltage-limiting SPDs connected in parallel, the amount of splitting impulse current and energy that flow through each SPDs is investigated as a function of the protective distance. As a result, the energetic coordination between cascaded SPDs is strongly dependent on the voltage protection level of SPDs and the protective distance. It was confirmed that the sharing of the energy between two cascaded SPDs and the limited voltage levels are appropriate when the voltage protection levels of both upstream and downstream SPDs are the same.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.4
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• pp.116-125
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• 2015

This paper presents experimental results obtained from actual installation conditions of surge protective devices (SPDs), with the aim of understanding the coordination of cascaded Class I and Class II SPDs. This paper also proposes effective methods for selecting and installing coordinating cascaded SPDs. The residual voltage of each SPD and the energy sharing of an upstream Class I tested SPD and a downstream Class II tested SPD were measured using a $10/350{\mu}s$ current wave. In coordinating a cascaded voltage-limiting SPD system, it was found that energy coordination can be achieved as long as the downstream SPD is a metal oxide varistor with a higher maximum continuous operating voltage than the upstream SPD; however, it is not the optimal condition for the voltage protection level. If the varistor voltage of the downstream SPD is equal to or lower than that of the upstream SPD, the precise voltage protection level is obtained. However, this may cause serious problems with regard to energy sharing. The coordination for energy sharing and voltage protection level is fairly achieved when the cascaded SPD system consists of two voltage-limiting SPDs separated by 3 m and with the same varistor voltage.

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.18-23
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• 2012

In this paper, a potable device application for DC-DC converter was designed for voltage protection circuit. Voltage protection circuit to offer the under voltage lock out and over voltage protection consists of a comparator and bais circuits were implemented using. XFAB 1um CMOS process, SPICE simulations was confirmed through the characteristics. Simulation results, under voltage lock out input voltage is 4.8 V higher when the turn-on and, 4.2 V less when turn-off. When the input voltage is low voltage is applied can be used to prevent malfunction of the circuit. Over voltage protection is 3.8 V reference voltage when the output voltage caused by blocking circuit prevents device destruction can be used to improve the stability and reliability. The virtual control circuits of the DC-DC converter connected. According to the results of the abnormal voltage, voltage protection circuit behavior was confirmed. The proposed voltage protection circuit of the DC-DC converter cell is useful are considered.

• ETRI Journal
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• v.38 no.2
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.6
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• pp.91-98
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• 2014

For the purpose of designing and applying the optimum surge protection scheme, multi-stage coordinated surge protective device(SPD) system is suitable to successfully fulfill its tasks; first, to divert a large amount of the transient energy, second, to clamp the overvoltage to the level below the withstand impulse voltage of the equipment to be protected. The length of SPD connecting leads shall be as short as possible. Long connecting leads will degrade the protection effect of SPDs. In this paper, the influences of the length of connecting leads on the energy sharing in a coordinated SPD system were investigated experimentally, and the simulation of determining the energy sharing and protection voltage level of each SPD depending on the length of connecting leads was carried out by using P-spice program. It was confirmed that the protection voltage level and energy sharing in coordinated SPD systems are strongly influenced by the length of connecting leads.