• ETRI Journal
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• v.17 no.2
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.1
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• pp.61-69
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• 2002

This paper describes a converting algorithm between programmable languages of a software PLU. It is based on IEC 61131-3 standard and PC. The proposed control logic is designed by the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 61131-3 Standard. The generation method of object file is proposed on five programmable language based on IEC 61131-3. It is represented as fo11ows; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using f code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ 6.0 and MFC on MS-windows NT 4.0.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.730-736
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• 1995

This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.33-36
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• 1994

The characteristics of the nonvolatile MONOS memory devices as the nitride thickness is scaled down while maintaining constant tunneling oxide thickness and blocking oxide thickness have been investigated in order to obtain the 5V-programmable E$^2$PROM. We have found that 1V memory window for a 5V programming voltage and 10 year data retention can be achieved in the scaled MONOS memory devices with a 50 blocking oxide, a 57 nitride and a 19 tunneling oxide.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.12
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• pp.667-673
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• 2006

Programmable electronic interlocking system plays key role in railway operation and is closely related to railway accidents, in which the programmable electronic controller of interlocking system may become sources. Redundant digital controllers are adopted as the interlocking controllers to prevent the accidents from the controllers being out of order. The redundant digital controllers being fault tolerant are realized through dual or triplex controllers. In this paper, we calculated safety and availability of the redundant digital controllers using Markov models, demonstrated key part to determine the availability ana the safety.

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.423-425
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• 1998

In this paper, a novel Programmable Signal Conditioner(PSC) for Thermo Couple(T/C) without variable-resistance is proposed. It is fabricated by using a fully digitalized error-correction and calibration algorithm. In signal processing of T/C, since the output voltage of T/C is nonlinear and its level is very low, the circuitry become very complicated to reduce the converting error and identify the true thermal voltage signal. The newly proposed PSC has compensation and calibration algorithm not using variable resistor. Moreover structure can be very simple and it has highly precise output characteristics.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1547-1550
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• 2002

Reconfigurable computing is a new computing paradigm which has more potential in terms of performance and flexibility. Reconfigurable computing systems are opening a new era in digital signal processing such as multimedia, communication and consumer electronics because they can filter data rapidly and excel at pattern recognition, image process- ing and encryption. Although many reconfigurable computing systems use a conventional programmable device, they carry several serious problems to be solved. This paper proposes a logic block architecture of programmable device suit-able for the reconfigurable computing. Compared to conventional logic blocks, our logic block can improve implementation density, efficiency and speed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.