• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.12
• /
• pp.953-958
• /
• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• Journal of Sensor Science and Technology
• /
• v.21 no.1
• /
• pp.21-27
• /
• 2012

In this study, we designed an embedded system for automatic condensation control(ESCC) of the car. This system heats the car glasses as and when it is needed that makes driving safer and convenient. The system was built on an ATmega128L central processing unit(CPU), using high-performance electrically erasable programmable read-only memory(EEPROM) complex programmable logic device(CPLD) ATF1504AS, using which an ESCC algorithm has been proposed. The source code was written in C language. The algorithm of work was written using the dew-point table. This system not only clears the condensation on the glass but also averts condensation. The designed ESCC system begins working once the input information comes close to the dew-point table information. This device enables a wider field of view, thereby increasing safety.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.413-414
• /
• 2012

Programmable Metallization Cell (PMC) memory, which utilizes electrochemical control of nanoscale quantities of metal in thin films of solid electrolyte, shows great promise as a future solid state memory. The technology utilizes the electrochemical formation and removal of metallic pathways in thin films of solid electrolyte. Key attributes are low voltage and current operation, excellent scalability, and a simple fabrication sequence. In this study, we investigated the nature of thin films formed by photo doping of Ag+ ions into chalcogenide materials for use in solid electrolyte of programmable metallization cell devices. We measured the I-V characteristics by field-effect of the device. The results imply that a Ag-rich phase separates owing to the reaction of Ag with free atoms from chalcogenide materials.

• Journal of Sensor Science and Technology
• /
• v.21 no.3
• /
• pp.235-239
• /
• 2012

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.06c
• /
• pp.220-222
• /
• 2006

본 논문은 안전등급 제어기기(Safety-Grade Programmable Logic Controller)에서 사용하는 프로세서모듈 운영체제에 대한 컴포넌트 시험에 대해 기술한다. 디지털 소프트웨어에 대한 NRC(Nuclear Regulatory Commission)의 지침에 따라 운영체제는 소프트웨어 생명주기에 따라 개발되고 있으며 요구사항과 설계명세, 그리고 구현코드를 가지고 다양한 시험을 수행하고 있다. 컴포넌트 시험은 구현된 코드가 테스트 커버리지를 만족하는 지 파악하는 시험이다. 이를 위해 설계명세서를 참조하여 시험대상을 구분하고 각각의 시험대상에 대한 시험항목을 세분화한 이후 시험방법과 절차, 그리고 시험환경을 구축한 후 컴포넌트 시험을 수행한다.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.4
• /
• pp.14-18
• /
• 1997

A design methodology of the analog current-mode and width programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by the 0.8$\mu\textrm{m}$ CMOS n-well single poly/double metal standard digital process. The integrator occupies the active chip area of 0.3$\textrm{mm}^2$. The experimental result illustrates a low power dissipation (1.0mW∼3.55 mW), 65dB of the dynamic range, and digitally and width programmability (10MHz∼30MHz) with an external digital 4 bit.

• Journal of Power System Engineering
• /
• v.8 no.1
• /
• pp.62-68
• /
• 2004

This paper describes a fault tolerant control in distributed PLC(Programmable Logic Controller) system to ensure reliability of controllers which have some faults simultaneously. First, the behavior of PLC is modeled as discrete expressions using Galois field. Then, we design the control laws for additional spare controllers to generate parity code with two dimensions. Finally, the algorithm for estimating normal output instead of abnormal output from the controllers with fault is suggested. Comparing to the traditional duplication method, the suggested method can reduce the number of spare controllers significantly to ensure control reliability. This method will be applied to an automatic system in order to increase reliability. Also, it can improve cost performance of the system.

• International Journal of Control, Automation, and Systems
• /
• v.4 no.5
• /
• pp.567-574
• /
• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• Proceedings of the IEEK Conference
• /
• 2002.06d
• /
• pp.183-186
• /
• 2002

In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.4
• /
• pp.142-151
• /
• 1996

This paper presents a new symmetrical routing architecture for FPGA and an efficient routing algorithm for the architecture. The routing architecture adopts the segmented wires and the improved switch modules. Segmetned wires construct routing channels which pass through the chip in vertical and horizontal directions. To maximize the utility of a track, a track in each switch module can be separated in two part using a programmable switch to route two different net. The proposed routing algorithm finds all assignable tracks for a given net and selects the best track from assignable tracks to minimize the number of programmable switches and the unused portion of the wire segments. In order to stabilize the perfomrance of the algorithm, the routing order is defined by weighted sum of the number of wire segment, the length of wire segmetn, and the number of pin. Experimental results show that routability is improved dramatically and the number of crossing switches are reduced about 40% compared with the previous works.