• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Korean Journal of Materials Research
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• v.19 no.9
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• The KIPS Transactions:PartD
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• v.18D no.1
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• pp.35-44
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• 2011

Memory errors can cause not only program malfunctions but also even unexpected system halt. Though a programmer checks memory errors, some memory errors with low occurrence frequency are missed to detect. In this paper, we propose a method for effectively detecting such memory errors using instruction transition diagrams through analyzing assembly codes obtained by disassembling an executable file. Out of various memory errors, local memory return errors, null pointer access errors and uninitialized pointer access errors are targeted for detection. When applying the proposed method to various programs including well-known open source programs such as Apache web server and PHP script interpreter, some potential memory errors are detected.

• Korean Journal of Biological Psychiatry
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• v.11 no.2
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• pp.155-164
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• 2004

Objective:The present study examined the association between basic neurocognitive functions and emotional recognition in chronic schizophrenia. Furthermore, to Investigate cognitive variable related to emotion recognition in Schizophrenia. Methods:Forty eight patients from the Yongin Psychiatric Rehabilitation Center were evaluated for neurocognitive function, and Emotional Recognition Test which has four subscales finding emotional clue, discriminating emotions, understanding emotional context and emotional capacity. Measures of neurocognitive functioning were selected based on hypothesized relationships to perception of emotion. These measures included:1) Letter Number Sequencing Test, a measure of working memory;2) Word Fluency and Block Design, a measure of executive function;3) Hopkins Verbal Learning Test-Korean version, a measure of verbal memory;4) Digit Span, a measure of immediate memory;5) Span of Apprehension Task, a measure of early visual processing, visual scanning;6) Continuous Performance Test, a measure of sustained attention functioning. Correlation analyses between specific neurocognitive measures and emotional recognition test were made. To examine the degree to which neurocognitive performance predicting emotional recognition, hierarchical regression analyses were also made. Results:Working memory, and verbal memory were closely related with emotional discrimination. Working memory, Span of Apprehension and Digit Span were closely related with contextual recognition. Among cognitive measures, Span of Apprehension, Working memory, Digit Span were most important variables in predicting emotional capacity. Conclusion:These results are relevant considering that emotional information processing depends, in part, on the abilities to scan the context and to use immediate working memory. These results indicated that mul- tifaceted cognitive training program added with Emotional Recognition Task(Cognitive Behavioral Rehabilitation Therapy added with Emotional Management Program) are promising.

• Journal of agricultural medicine and community health
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• v.48 no.1
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• pp.1-12
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• 2023

Objective: The purpose of this study was to identify factors associated with subjective memory impairment in patients with diabetes mellitus in a metropolitan city. Methods: The subjects of this study were 351 patients with diabetes mellitus aged 50 and over from five districts of Gwangju who participated in the 2018 Community Health Survey. We analyzed general characteristics, health-related behaviors and health related conditions and subjective experience of memory impairment. To find factors associated with subjective memory impairment, the chi-square test and multiple logistic regression analysis were used. Results: Of all subjects, 31.3% was reported subjective experience of memory impairment. The odds ratios (ORs; 95% confidence interval (CI)) for subjective memory impairment according to age were statistically significant at 1.9 (0.9-4.3) in patients in 60s and 2.2 (1.1-4.7) in patients in beyond 70s compared to those in 50s. The OR (95% CI) of ex-smoker compared to the non-smoker was 0.3 (0.8-0.9). The OR (95% CI) of depressive symptom compared to no depressive symptoms was 4.9 (95% CI: 1.8-13.7). Conclusion: In this study, subjective memory impairment in patients with diabets mellitus was associated with age, smoking, and depressive symptoms. Based on the results of this study, subjective memory impairment should be detected early through periodic cognitive function evaluation for elderly patients with diabetes mellitus, and a program for healthy cognitive function should be included in diabetes management program.

• Journal of Gifted/Talented Education
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• v.7 no.1
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• pp.51-76
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• 1997

The purpose of this study was to investigate the effects of Structure of Intellect( SOI) program for children. To achieve this purpose, 81 second grade children were sampled in a elementary school located In Seoul-city and randomly assigned to the experimental group and control group The SO1 training program were treated to the experimental group for 10 weeks, and the 'Thinking Abilities Test developed by Korea Creativity Research Institute were administered to them for pre-test and post-test. The collected data were analyzed by t-test for comparing the group means of experimental group and control group 'I'he results of this study were as follows : Firstly ere were statistically significant differences between experimental group and control group on the post-test scores of arithmetic[t(79)=2.73p,< .01] and visual memory[t(79)-3.68,p <.001]. The mean scores of experimental group(M=8.63) u ere higher than that of control group(Mz7.34) on arithmetic, and the mean scores to experimental group(M=16.68) were higher than that of control group(M=15 32) on visual memory Secondly there were no statistically significant differences between experimental group and control group on the post-test scores of logistic thinking abilities[t(79)=0.22, p>.05] and abstract thinking abilities[t(79)-0.22, p>.051. Thirdly, the post-test scores of visual memory and logical thinking abilities were more increased in the low intelligence group than the high intelligence group. This result showed that the SO1 program were more effective for the low intelligence group. Fourthly, the post-test scores of visual memory and logical thinking abilities were more increased in the low achievement group than the high achievement group. This result showed that the SO1 program were more effective for the low achievement group.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.1-11
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• 2020

In this paper, we present a technique that executes MPI parallel programs, that are developed on processor-centric computer architecture, more efficiently on memory-centric computer architecture without program modification. The technique we present here improves performance by replacing low-speed data communication over the network of MPI library functions with high-speed data communication using the property called fast large shared memory of memory-centric computer architecture. The technique we present in the paper is implemented in two programs. The first program is a modified MPI library called MC-MPI-LIB that runs MPI parallel programs more efficiently on memory-centric computer architecture preserving the semantics of MPI library functions. The second program is a simulation program called MC-MPI-SIM that simulates the performance of memory-centric computer architecture on processor-centric computer architecture. We developed and tested the programs on distributed systems environment deployed on Docker based virtualization. We analyzed the performance of several MPI parallel programs and showed that we achieved better performance on memory-centric computer architecture. Especially we could see very high performance on the MPI parallel programs with high communication overhead.

• 한국전산유체공학회:학술대회논문집
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• 2002.05a
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• pp.158-163
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• 2002

In the present study a 3D data visualization and analysis program with stereoscopic viewing is introduced. The GUI of the program is based on Qt-library, while all the graphic rendering is performed with OpenGL library. The program allocates memory dynamically according to the data size so that the problem size is only limited by the computer's hardware memory. The stereoscopic viewing is realized by carefully-calibrated projection and color-masking of red and blue color for the left and right eye, and the only hardware needed for the stereoscopic visualization of 3D data is a cheap and easily-available red/blue glasses. Further work for addition of more functions and options to the present program will be continued.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.395-396
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• 2008

There is difficulty in predicting the program efficiency of NOR type nonvolatile memory device adopting channel hot electron injection (CHEI) as program operation mechanism accurately since MOSFET on SOI has floating body. In this study, the dependence of program efficiency for SOI nonvolatile memory device of 200 nm channel length on SOI depletion conditions, partial depletion and full depletion, was quantitatively investigated with the aid of numerical device simulation [1].

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.