• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.6
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• pp.177-184
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• 2015

This paper proposes a minimum-power scheduling scheme of real-time parallel tasks while meeting deadlines of the real-time tasks on DVFS-enabled multicore processors. The proposed scheme first finds a floating number of processing cores to each task so that the computation load of all processing cores would be equalized. Next the scheme translates the found floating number of cores into a natural number of cores while maintaining the computation load of all cores unchanged, and allocates the translated natural number of cores to the execution of each task. The scheme is designed to minimize the power consumption of the frequency-sharing multicore processor operating with the same processing speed at an instant time. Evaluation shows that the scheme saves up to 38% power consumption of the previous method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.617-619
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• 2015

If you are sharing a manual created in small organizations, webzine, and other publications, the original or a PDF file or a file created with a word processor to facilitate the sharing of publications and the members of the organization through the data downloaded from the mail or the web most have been used. However, users often do not want to see one online source or download the file. In this paper, If the original file of the word processor on windows-based systems, in this paper, only the upload progress in implementing e-book publishing system automatically e-book system is viewable on the Web by providing a range of information for users and small members and we propose a system construction that can be shared.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11A
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• pp.1120-1127
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• 2007

In this paper, we propose a generalized processor sharing - dynamic resource allocation (GPS-DRA) scheme which allocates the required amount of resources to each hop dynamically in cellular-based multi-hop systems. In the hybrid-distributed system considered in this paper, a central controller such as a base station (BS) should allocate resources properly to each hop. However, due to changing channel condition with time, it is difficult to allocate as much amount of resources as each hop needs for transmission. GPS-DRA scheme allocates the required amount of resources dynamically to each hop based on the amount of resources used in previous frames by each hop. The amount of control overhead generated by GPS-DRA scheme can be very small because a central controller doesn't need to collect all link information for resource allocation. Our simulation results show that channel utilization increased about 16% and cell capacity increased about 65% compared to those of fixed resource allocation (FRA) scheme.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.147-155
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• 2005

For the last several decades, many researches have been performed to distribute bandwidth fairly between sessions. In this problem, the most important challenge is to realize a scalable implementation and high fairness simultaneously. Here high fairness means that bandwidth is distributed fairly even in short time intervals. Unfortunately, existing scheduling algorithms either are lack of scalable implementation or can achieve low fairness. In this paper, we propose a scheduling algorithm that can achieve feasible fairness without losing scalability. The proposed algorithm is a Hierarchical Deficit Round-Robin (H-DRR). While H-DRR requires a constant time for implementation, the achievable fairness is similar to that of Packet-by-Packet Generalized Processor Sharing(PGPS) algorithm. PGPS has worse scalability since it uses a sorted-priority queue requiring O(log N) implementation complexity where N is the number of sessions.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.445-454
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• 2006

Almost of industrial measuring instruments usually are equipped only with serial communication devices. In order to connect these instruments to internet, we implement an embedded translator. This device has the hardware components composed of one WAN port, two LAN ports, and two UARTs, and functions as a communication translator between serial and internet communication. it also provides web-based monitoring function that is absent from existing serial-to-ethernet converter. The hardware is implemented using the KS8695 network processor which s an ARM922T as processor core. We have installed the boa web server and utilized the CGI function for internet-based remote control, added the IP sharing function which allows the network with private IP addresses to access the internet, and developed a serial-to-ethernet translation program. Finally, we show an application example of the developed translator that remotely monitors the solar energy production system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.91-94
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• 2012

This paper describes an efficient implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit specified in the standard. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 33,218 gates and the estimated throughput is about 640 Mbps at 100 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• KIISE Transactions on Computing Practices
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• v.22 no.1
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• pp.1-7
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• 2016

When multiple applications are running concurrently on a multi-processor system, interferences between applications make it difficult to guarantee real-time constraints. We propose a novel interference analysis technique that allows sharing of share processors among dataflow applications, while satisfying real-time constraints. Based on the interference analysis, we develop a co-scheduling technique that aims to minimize the resource usage. Compared to an existent technique that involves converting application graphs to real-time tasks, the proposed technique shows better results in terms of resource usage, especially when it is applied to applications with tight time constraints.