• 대한수학회보
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• 제47권6호
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• pp.1251-1258
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• 2010

For an M/G/1 processor-sharing queue with batch arrivals, Avrachenkov et al. [1] conjectured that the conditional mean sojourn time is concave. However, Kim and Kim [5] showed that this conjecture is not true in general. In this paper, we show that this conjecture is true if the service times have a hyperexponential distribution.

• Journal of applied mathematics & informatics
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• 제42권2호
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• pp.291-303
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• 2024

In this paper, we consider a feedforward network of overloaded multiclass processor sharing queues and we give a fluid model solution under the condition that the system is initially empty. The main theorem of the paper provides sufficient conditions for a fluid model solution to be linear with time. The results are illustrated through examples.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1221-1224
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• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• 정보처리학회논문지A
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• 제10A권4호
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• pp.347-356
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• 2003

DCT 알고리즘은 내적을 효율적으로 처리할 수 있는 하드웨어 구조가 필수적이다. 내적 연산을 위한 기존의 방법들은 하드웨어 복잡도가 높기 때문에, 이론 줄이기 위한 방법으로 연산 공유 승산기가 제안되었다. 하지만 기존의 연산 공유 승산기는 전처리기 및 선택기의 비효율적 구조로 인한 성능저하의 문제점을 가지고 있다. 본 논문에서는 새로운 연산 공유 승산기를 제안하고 이를 1차원 DCT 프로세서에 적용하여 구현하였다. 연산 공유 승산기의 구조 및 논리 합성 비교 시 새로운 승산기는 기존에 비해 효율적인 하드웨어 구성이 가능함을 확인하였고, 1차원 DCT 프로세서 설계 시 기존 구현 방식들에 비해 우수한 성능을 나타내었다.

• Journal of applied mathematics & informatics
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• 제15권1_2호
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• pp.511-525
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• 2004

we model communication and computer systems that process interactive and several and several types of background jobs. The scheduling policy in use is to share the processor among all interactive jobs and, at most, one background job of each type at a time according to the process sharing discipline. Background jobs of each type are served on a first-come-first-served basis. Such scheduling policy is called Processor Sharing with Background jobs (PSBJ). In fact, the PSBJ policy is commonly used on many communication and computer systems that allow interactive usage of the systems and process certain jobs in a background mode. In this paper, the stability conditions for the PSBJ policy are given and proved. Since an exact analysis of the policy seems to be very difficult, an approximate analytic model is proposed to obtain the average job sojourn times. The model requires the solution of a set of nonlinear equations, for which an iterative algorithm is given and its convergence is proved. Our results reveal that the model provides excellent estimates of average sojourn times for both interactive and background jobs with a few percent of errors in most of the cases considered.

• 응용통계연구
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• 제22권3호
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• pp.541-551
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• 2009

Generalized processor sharing(GPS) service policy is a scheduling algorithm to allocate the bandwidth of a queueing system with multi-class input traffic. In a queueing system with single-class traffic, the stationary queue length becomes larger stochastically when the bandwidth (i.e. the service rate) of the system decreases. For a given GPS server, we consider the similar problem to this. We define the monotonicity for the head of the line processor sharing(HLPS) servers in which the units in the heads of the queues are served simultaneously and the bandwidth allocated to each queue are determined by the numbers of units in the queues. GPS is a type of monotonic HLPS. We obtain the HLPS server whose queue length of a class stochastically bounds upper that of corresponding class in the given monotonic HLPS server for all classes. The queue lengths process of all classes in the obtained HLPS server has the stationary distribution of product form. When the given monotonic HLPS server is GPS server, we obtain the explicit form of the stationary queue lengths distribution of the bounding HLPS server. Numerical result shows how tight the stochastic bound is.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1994년도 추계학술발표회 및 정기총회
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• 정보과학회지
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• 제5권1호
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• pp.04-10
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• 1987

本 論文은 단일 processor를 가진 computer time sharing system의 運用 에 關한 것이다. 서로 다른 K 종류의 task들이 各各 獨立的이고 time-homojeneous한 Poisson分布를 따라 System에 들어 오고 있다. 또한, task 가 配當된 quantum동안 process를 받고 난후 이미 주어진 確率에 의해, 써어비스 를 完了받고 System을 離脫하기도 하고, 未完結된 경우 다른 種類의 task로 바뀌 어져 다시 process를 받기 爲해 待期한다고 한다. 이러한 여러종류의 task를 相對 로 한 time sharing model에서는 各種類의 完結에 必要한 process time의 길이에 의해 各種類의 順位(priority)가 一方的으로 決定된 것이 通例이었다. 本 硏究에서 는 各 種類의 順位를 결정하는데 있어서, 좀더 現實的인 諸條件을 반영키 위해, 各種類의 完決에 要하는 process time의 길이 뿐만 아니라, 그들의 重要度 그리고 또 緊急度까지도 고려한 새로운 Schedulign rule을 개발하였다. 또한 이 새로운 Scheduling rule에 의해 順位를 決定하는 Algorithm도 수록하였다.

• ETRI Journal
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• 제32권1호
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 한국콘텐츠학회논문지
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• 제5권3호
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• pp.183-191
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• 2005

송신자 개시 부하 균형 알고리즘에서는 전체 시스템이 과부하일 때 송신자(과부하 프로세서)가 부하를 이전하기 위해 수신자(저부하 프로세서)를 발견할 때까지 불필요한 이전 요청 메시지를 계속 보내게 된다. 따라서 이 같은 상황에서는 저부하 상태인 수신자 프로세서로부터 승인 메시지를 받기까지 불필요한 프로세서 간 통신으로 인하여 프로세서의 이용률이 저하되고 또한 태스크의 처리율이 낮아지는 문제점이 발생한다. 본 논문에서는 이질형 분산 시스템에서의 동적 부하 균형을 위해 유전 알고리즘을 기반으로 하는 접근 방법을 제안한다. 이 기법에서는 불필요한 요청 메시지를 줄이기 위해 요청 메시지가 전송될 프로세서들이 제안된 유전 알고리즘에 의해 결정된다.