• Journal of Institute of Control, Robotics and Systems
• /
• v.7 no.1
• /
• pp.1196-1204
• /
• 2001

In this paper, a new architecture of operating software associated with the component-based method is proposed. The proposed architecture comprises 문 execution module and a decision-making module. In order to make effective development and maintenance, the execution module is divided into three components. The components are referred to as Symbol, Gateway, and Control, respectively: The symbol component is for the GUI environments and the standard interfaces; the gateway component is for the network communication and the structure of asynchronous processes; the control component is for the asynchronous processing and machine setting or operations. In order to verify the proposed architecture, and off-line version of operating software is made, and its steps are as follows; I) Make virtual execution modules for the manufacturing devices such as dual-arm robot, handling robot, CNC, and sensor; ii) Make decision-making module; iii) Integrate the modules and GUI using a well-known development tools such as Microsofts Visual Basic; iv) Execute the overall operating software to validate the proposed architecture. The proposed software architecture in this paper has the advantages such as independent development of each module, easy development of network communication, and distributed processing of resources, and so on.

• ETRI Journal
• /
• v.32 no.3
• /
• pp.380-389
• /
• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• Journal of Information Processing Systems
• /
• v.18 no.2
• /
• pp.188-196
• /
• 2022

Recently, neural architecture search (NAS) has received increasing attention as it can replace human experts in designing the architecture of neural networks for different tasks and has achieved remarkable results in many challenging tasks. In this study, a path-based computation neural architecture encoder (PCE) was proposed. Our PCE first encodes the computation of information on each path in a neural network, and then aggregates the encodings on all paths together through an attention mechanism, simulating the process of information computation along paths in a neural network and encoding the computation on the neural network instead of the structure of the graph, which is more consistent with the computational properties of neural networks. We performed an extensive comparison with eight encoding methods on two commonly used NAS search spaces (NAS-Bench-101 and NAS-Bench-201), which included a comparison of the predictive capabilities of performance predictors and search capabilities based on two search strategies (reinforcement learning-based and Bayesian optimization-based) when equipped with different encoders. Experimental evaluation shows that PCE is an efficient encoding method that effectively ranks and predicts neural architecture performance, thereby improving the search efficiency of neural architectures.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.5
• /
• pp.1358-1370
• /
• 1997

Client-Sever-Comptuing is now recognized as the most powerful and flexible computing mode of the future.Many companies have already commited significant amount of their corporate IS resources to building the cli-ent-server computing environment.Despite this active interst and commitment,however,results from such cli-ent-sever projects are far from being convincing Among the many factors,we suspect,we supect that the less than less than satisfac-tory client-server experiences are perhaps due to the company's lack of underxtanding its essertial information processing characteristics.We analyze five client-server archiedctures in temrs of seven IS-related crieria.We then develop a contin-gency model to match company's information processing chracteristics to the ideal client-server architecture for the firm.Based on the client-server architecture analysis from the previous step. we recommend specific im-plementation strategies for each-server architecture selected. Finally,on an exploratory level,we look into the three client-server implmentation cases to cases to check the validity of our contingency model.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.2
• /
• pp.45-50
• /
• 2017

Micro-service Architecture is a service architecture optimized for large-scale distributed systems such as real-time realistic broadcasting systems, so that are fiercely adopted by Global leading service platform vendors such as Netflix and Twitter due to the merit of horizontal performance scalability enabling the scale-out technique. In addition, micro-service architecture makes it possible to execute image processing and real-time data analysis using an asynchronous-based processing that are difficult to handle in Web API such as REST. In this paper, an event stream processing framework applicable to asynchronous based micro services is proposed in the sense that the accountability of event processing order is not guaranteed in the events such as IoT sensor data analysis or cloud-based image editing because these are the situations where the real-time media editing generates multiple event streams and asynchronous processes in the platform.

• The KIPS Transactions:PartA
• /
• v.13A no.3 s.100
• /
• pp.191-198
• /
• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• The KIPS Transactions:PartB
• /
• v.13B no.3 s.106
• /
• pp.223-230
• /
• 2006

A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform ail of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA(Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.6
• /
• pp.55-64
• /
• 2017

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

• Proceedings of the KIEE Conference
• /
• 1986.07a
• /
• pp.473-477
• /
• 1986

• Journal of Institute of Control, Robotics and Systems
• /
• v.14 no.7
• /
• pp.720-725
• /
• 2008

This paper proposes a system architecture for USN with a service robot to provide more active assisted living services for elderly persons by monitoring their mental and physical well-being with USN environments at home, hospital, or silver town. Sensors embedded in USN are used to detect preventive measures for chronic disease. Logged data are transferred to main controller of a service robot via wireless channel in which the analysis of data is performed. For the purpose of handling emergency situations, it needs real-time processing on gathering variety sensor data, routing algorithms for sensor nodes to a moving sink node and processing of logged data. This paper realized multi-hop sensor network to detect user movements with biometric data transmission and performed algorithms on Xenomai, a real-time embedded Linux. To leverage active sensing, a mobile robot is used of which task was implemented with a priority to process urgent data came from the sink-node. This software architecture is anticipated to integrate sensing, communication and computing with real-time manner. In order to verify the usefulness of a proposed system, the performance of data transferring and processing on a real-time OS with non real-time OS is also evaluated.