• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.84-89
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop dual split ring resonator is presented for reducing the phase noise. The square-shaped dual split ring resonator having the form of the microstrip square open loop is investigated to reduce the phase noise. Compared with the microstrip square open loop resonator and the microstrip square open loop split ring resonator as well as the conventional microstrip line resonator, the microstrip square dual split ring resonator has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of -123.2~-122.0 dBc/Hz @ 100 kHz in the tuning range, 11.74~11.75 GHz. The figure of merit (FOM) of this VCO is-214.8~-221.7 dBc/Hz dBc/Hz @ 100 kHz in the same tuning range. Compared with VCO using the conventional microstrip line resonator, VCO using microstrip square open loop resonator, the phase noise of VCO using the proposed resonator has been improved in 26 dB, 10 dB, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.79-84
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• 2007

In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.13-21
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• 1997

In this paper, the oscillator type active antenna used as an element of active phased array antenna is designed and fabricated using slot coupling. The radiating element and active circuit are fabricated on each layer respectively and coupled electromagnetically through slot on the ground plane. This structure can solve the problems such as narrow bandwidth of microstrip antenna, spurious radiation by active circuits, and spaces for integration of the feeding circuits which are caused by integrating antennas with oscillator circuits in the same layer. The active antenna in this paper, the oscillation frequency can be tuned linearly by controlling the drain bias voltage of FET. The frequency tuning range is between 12.37 GHz to 12.65 GHz when bias voltage is varied from 3V to 9V, thus frequency tuning bandwidth is 280 MHz (2.24%). The output power of antenna is uniform within 5dB over frequency tuning range. Therefore this active antenna can be used as an element of linear or planar active phased array antennas.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.12
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• pp.1380-1393
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• 2010

This paper presents a design, fabrication and the test results of planar active electronically scanned array(AESA) radar prototype for airborne fighter applications using transmit/receive(T/R) module hybrid technology. LIG Nex1 developed a AESA radar prototype to obtain key technologies for airborne fighter's radar. The AESA radar prototype consists of a radiating array, T/R modules, a RF manifold, distributed power supplies, beam controllers, compact receivers with ADC(Analog-to-Digital Converter), a liquid-cooling unit, and an appropriate structure. The AESA antenna has a 590 mm-diameter, active-element area capable of containing 536 T/R modules. Each module is located to provide a triangle grid with $14.7\;mm{\times}19.5\;mm$ spacing among T/R modules. The array dissipates 1,554 watts, with a DC input of 2,310 watts when operated at the maximum transmit duty factor. The AESA radar prototype was tested on near-field chamber and the results become equal in expected beam pattern, providing the accurate and flexible control of antenna beam steering and beam shaping.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2015.10a
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• pp.279-282
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• 2015

Fisheries development of the basic law pursuant to article 15 (marine safety management, etc.) one of maritime safety and maritime traffic facilities nationwide network of DGPS in accordance with the building maximize infrastructure utilization and country. Source technology has been improving steadily raised for the benefit daegukmin. In particular, look at the type of product for the marine supply medium-wave receiver Performance products that satisfy most of the IMO Advisory. The antenna and receiver are separate structural supply for some integrated model with a very high Rather it is used as a portable receivers for marine positioning cheap integrated model development is needed. Correction of satellite navigation receivers for the current Marine GPS module, medium-wave modules can be developed one low cost Integrated in independent operating environments do not support the model development done look at what the problem is 285kHz ~ 315kHz in DGPS Beacon receiver structure using a medium wave or Beacon The medium-wave antenna and a GPS receiver signal to noise ratio was studied GPS signal attenuation on the DGPS performance looked at each GPS manufacturer medium-wave signal-to-noise ratio and normalized impact by GPS manufacturers noise power ratio per bandwidth for medium-wave GPS signals affect it was implemented to improve performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• Korean Chemical Engineering Research
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• v.49 no.6
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• pp.816-822
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• 2011

Pervaporation is known to be a low energy consumption process since it needs only an electric power to maintain the permeate side in vacuum. Also, the pervaporation is an environmentally clean technology because it does not use the third material such as an entrainer for either an azeotropic distillation or an extractive distillation. In this study, Silicalite-1 particles are hydrothermally synthesized and polydimethylsiloxane(PDMS)-zeolite composite membranes are prepared with a mixture of synthesized Silicalite-1 particles and PDMS-polymer. They are used to separate n-butanol from its aqueous solution. Pervaporation characteristics such as a permeation flux and a separation factor are investigated as a function of the feed concentration and the weight % of Silicalite-1 particles in the membrane. A 1,000 $cm^3$ aqueous solution containing butanol of low mole fraction such as order of 0.001 was used as a feed to the membrane cell while the pressure of the permeation side was kept about 0.2~0.3 torr. When the butanol concentration in the feed solution was 0.015 mole fraction, the flux of n-butanol significantly increased from 14.5 g/ $m^2$/hr to 186.3 g/$m^2$/hr as the Silicalite-1 content increased from 0 wt% to 10 wt%, indicating that the Silicalite-1 molecular sieve improved the membrane permselectivity from 4.8 to 11.8 due to its unique crystalline microporous structure and its strong hydrophobicity. Consequently, the concentration of n-butanol in the permeate substantially increased from 0.07 to 0.15 mole fraction. This composite membrane could be potentially appliable for separation of n-butanol from insitu fermentation broth where n-butanol is produced at a fairly low concentration of 0.015 mole fraction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.405-419
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• 2012

In this paper, we propose a joint base station(BS) and relay precoders design in multi-relay aided multi-user all-multiple-input multiple-output(MIMO) system. The design criterion is to minimize user sum mean square error(SMSE) with relay sum power constraint(RSPC) where only local channel state information(CSI)s are available at relays. Local CSI at a relay is defined as the CSI of the channel which the relay itself accesses, out of among all the 1st hop and the 2nd hop channel in the system. With BS precoder structure which is concatenated with block diagonalization(BD) precoder, each relay can determine its own precoder using only local CSI. Proposed scheme is based on sequential iteration of two stages; stage 1 determines BS precoder and relay precoders jointly with SMSE duality, and stage 2 determines user receivers. Proposed scheme can be demonstrated theoretically to be always converge. We verify that proposed scheme outperforms simple amplify-and-forward(SAF), MMSE relay, and proposed schemes in [1] in terms of both SMSE and sum-rate performances.