• 대한전기학회논문지:시스템및제어부문D
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• 제53권9호
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• Journal of Information Processing Systems
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• 제16권6호
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• pp.1343-1358
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• 2020

In the stagewise arithmetic orthogonal matching pursuit algorithm, the weak threshold used in sparsity estimation is determined via maximum iterations. Different maximum iterations correspond to different thresholds and affect the performance of the algorithm. To solve this problem, we propose an improved variable weak threshold based on the stagewise arithmetic orthogonal matching pursuit algorithm. Our proposed algorithm uses the residual error value to control the weak threshold. When the residual value decreases, the threshold value continuously increases, so that the atoms contained in the atomic set are closer to the real sparsity value, making it possible to improve the reconstruction accuracy. In addition, we improved the generalized Jaccard coefficient in order to replace the inner product method that is used in the stagewise arithmetic orthogonal matching pursuit algorithm. Our proposed algorithm uses the covariance to replace the joint expectation for two variables based on the generalized Jaccard coefficient. The improved generalized Jaccard coefficient can be used to generate a more accurate calculation of the correlation between the measurement matrixes. In addition, the residual is more accurate, which can reduce the possibility of selecting the wrong atoms. We demonstrate using simulations that the proposed algorithm produces a better reconstruction result in the reconstruction of a one-dimensional signal and two-dimensional image signal.

• 정보보호학회논문지
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• 제26권1호
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• pp.5-15
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• 2016

전력 분석 공격은 공격자가 암호 알고리즘이 수행되는 동안 발생하는 전력 신호를 분석하여 비밀정보를 알아내는 분석 기법이다. 이러한 부채널 공격의 대응기법으로 널리 알려진 방법 중 하나는 마스킹 기법이다. 마스킹 기법은 크게 불 마스킹 형태와 산술 마스킹 형태의 두 종류로 나뉜다. 불 연산자와 산술 연산자를 사용하는 암호 알고리즘의 경우, 연산자에 따라 마스킹의 형태를 변환하는 알고리즘으로 마스킹 기법을 적용 가능하다. 본 논문에서는 기존의 방식보다 더 적은 비용의 저장 공간을 이용하는 산술 마스킹에서 불 마스킹 변환 알고리즘을 제안한다. 제안하는 변환 알고리즘은 마스킹의 최하위 비트(LSB)의 경우 불 마스킹과 산술 마스킹이 같음을 이용하여 변환하려는 비트 크기와 같은 크기만큼 저장 공간을 사용하여 참조 테이블을 구성한다. 이로 인해 기존의 변환 알고리즘과 비교해 성능 저하 없이 더 적은 비용으로 변환 알고리즘을 설계할 수 있다. 추가로 제안하는 기법을 LEA에 적용하여 기존의 기법보다 최대 26.2% 성능향상을 보였다.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2005년도 Proceedings of ISRS 2005
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• pp.678-682
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• 2005

IETF suggested AAA for safe and reliable user authentication on various network and protocol caused by development in internet and increase in users. Diameter standard authentication system does not provide mutual authentication and non-repudiation. AAA authentication system using public key was suggested to supplement such Diameter authentication but application in mobile service control nodes is difficult due to overhead of communication and arithmetic. ID based AAA authentication system was suggested to overcome such weak point but it still has the weak point against collusion attack or forgery attack. In this thesis, new ID based AAA authentication system is suggested which is safe against collusion attack and forgery attack and reduces arithmetic quantity of mobile nodes with insufficient arithmetic and power performance. In this thesis, cryptological safety and arithmetical efficiency is tested to test the suggested system through comparison and assessment of current systems. Suggested system uses two random numbers to provide stability at authentication of mobile nodes. Also, in terms of power, it provides the advantage of seamless service by reducing authentication executing time by the performance of server through improving efficiency with reduced arithmetic at nodes.

• Wind and Structures
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• 제19권5호
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• pp.505-522
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• 2014

While effects of the atmospheric boundary layer flow on engineering infrastructure are more or less known, some local transient winds create difficulties for structures, traffic and human activities. Hence, further research is required to fully elucidate flow characteristics of some of those very unique local winds. In this study, important characteristics of observed vertical velocity profiles along the main wind direction for the gusty Bora wind blowing along the eastern Adriatic coast are presented. Commonly used empirical power-law and the logarithmic-law profiles are compared against unique 3-level high-frequency Bora measurements. The experimental data agree well with the power-law and logarithmic-law approximations. An interesting feature observed is a decrease in the power-law exponent and aerodynamic surface roughness length, and an increase in friction velocity with increasing Bora wind velocity. This indicates an urban-like velocity profile for smaller wind velocities and rural-like velocity profile for larger wind velocities, which is due to a stronger increase in absolute velocity at each of the heights observed as compared to the respective velocity gradient (difference in average velocity among two different heights). The trends observed are similar during both the day and night. The thermal stratification is near neutral due to a strong mechanical mixing. The differences in aerodynamic surface roughness length are negligible for different time averaging periods when using the median. For the friction velocity, the arithmetic mean proved to be independent of the time record length, while for the power-law exponent both the arithmetic mean and the median are not influenced by the time averaging period. Another issue is a large difference in aerodynamic surface roughness length when calculating using the arithmetic mean and the median. This indicates that the more robust median is a more suitable parameter to determine the aerodynamic surface roughness length than the arithmetic mean value. Variations in velocity profiles at the same site during different wind periods are interesting because, in the engineering community, it has been commonly accepted that the aerodynamic characteristics at a particular site remain the same during various wind regimes.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.856-859
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• 2002

This paper proposes a high-performance VLSl architecture using distributed arithmetic for higher-order FIR filters with complex coefficients. For the purpose of realizing high sampling rate with small latency in high-order filters, we apply distributed arithmetic[1］. Moreover, in order to decrease drastically the power dissipation, the structure applying not ROM's but optimum function circuits which we have previously proposed, is utilized［2]［3］. However, this structure increases in the number of adders as compared to the conventional structure applying ROM's. In order to realize a more effective method for further higher-order filter, we propose newly an implementation applying two methods which have large effects on the unit using the adders. First , we propose an implementation applying SFAs(Serial Full Adders) and SFSs(Serial Full Subtractors). Second, we propose a structure applying proposed 4-2 adders. Finally, it is shown that the proposed architecture is an effective way to realize low power dissipation and small latency while the sampling rate is kept constant for further higher-order filters with complex coefficients.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• 한국인터넷방송통신학회논문지
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• 제20권1호
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• pp.101-106
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• 2020

본 논문은 채널에서 발생되는 부호간 간섭을 줄일 수 있는 QE-MMA 적응 등화 알고리즘의 성능 개선을 위하여 varying stepsize를 적용한 VS-QE-MMA (Varying Stepsize-Quantized Error-MMA)에 관한 것이다. 송신 신호의 고차 통계치와 오차 신호의 부호만을 이용하는 SE-MMA에서 오차 신호의 크기를 power-of-two 연산을 적용하여 탭 계수 갱신시 필요한 승산과 감산을 천이와 감산만으로 대체하여 H/W 응용을 용이하도록 QE-MMA가 등장하였다. QE-MMA는 이와 같이 연산량의 단순화에 의한 적응 등화 성능이 열화되므로 이를 개선하기 위하여 제안 방식인 VS-QE-MMA에서는 적응을 위한 고정 stepsize를 오차 신호의 비선형 변환에 의한 varying stepsize를 적용하였다. 동일한 채널과 신호대 잡음비에서 제안 방식이 기존 QE-MMA보다 개선된 성능을 얻을 수 있음을 시뮬레이션으로 확인하였다. 시뮬레이션 결과 VS-QE-MMA가 QE-MMA보다 모든 성능 지수에서 우월하였으며, 신호대 잡음비가 10dB 이상일 때 varying stepsize의 효과를 얻을 수 있음을 확인하였다.

• 한국인터넷방송통신학회논문지
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• 제21권1호
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• pp.55-60
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• 2021

본 논문은 시분산 채널에서 발생되는 비선형 찌그러짐에 의한 부호간 간섭을 줄일 수 있는 QE-MMA 적응 등화알고리즘에서 양자화 비트수와 stepsize에 의한 성능 평가에 관한 것이다. QE-MMA는 송신 신호 고차 통계치와 오차신호 부호만을 이용하는 SE-MMA에서 오차 신호의 크기를 power-of-two 연산을 적용하여 탭 계수 갱신 시 필요한 승산과 가산을 천이와 가산만으로 대체하여 H/W 응용을 용이하도록 제안되었다. 그러나 QE-MMA에서 오차의 부호를 얻기 위한 오차 신호의 발생 시 stepsize와 양자화기 비트수에 의해 적응 등화 성능이 상이하게 되며, 이를 시뮬레이션으로 확인하였다. 시뮬레이션 결과 QE-MMA 적응 알고리즘의 성능에서 정상 상태에 도달하기 위한 수렴 속도는 stepsize에 의해 결정되며 정상 상태 이후의 잔여량은 양자화 비트수에 의해 결정됨을 확인하였다.