• Title/Summary/Keyword: power-efficient design

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Double-Loop Coil Design for Wireless Power Transfer to Embedded Sensors on Spindles

  • Chen, Suiyu;Yang, Yongmin;Luo, Yanting
    • Journal of Power Electronics
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    • v.19 no.2
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    • pp.602-611
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    • 2019
  • The major drawbacks of magnetic resonant coupled wireless power transfer (WPT) to the embedded sensors on spindles are transmission instability and low efficiency of the transmission. This paper proposes a novel double-loop coil design for wirelessly charging embedded sensors. Theoretical and finite-element analyses show that the proposed coil has good transmission performance. In addition, the power transmission capability of the double-loop coil can be improved by reducing the radius difference and width difference of the transmitter and receiver. It has been demonstrated by analysis and practical experiments that a magnetic resonant coupled WPT system using the double-loop coil can provide a stable and efficient power transmission to embedded sensors.

The design of high-voltage rectangular waveform generator (저주파 변압기를 이용한 구형파 증폭시스템)

  • Lee, B.H.;Choi, W.G.;Lim, J.K.;Lee, B.W.
    • Proceedings of the KIEE Conference
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    • 1999.07e
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    • pp.2152-2154
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    • 1999
  • In this paper, we suggested the design rule of high-voltage rectangular waveform generator working in low frequency domain (5Hz $\sim$ 60Hz). Most of the commonly used power electronic switching devices have voltage ratings up to several kV. So it is difficult to design and fabricate high-voltage switching systems with the power electronic devices alone. We have combined IGBTC(1200V, 50A) with the specially designed transformer to get the high-voltage rectangular waveforms up to 40kV. In this work. next two things are the main factors. The first one is design of transformer working low-frequency domain close to 5Hz. And the second one is additional voltage source to floating the transformer voltage output. As a result, we can get frequency-variable and high-voltage rectangular voltage waveform and this can be a more efficient power source of sandpaper manufacturing process.

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Optimum design and analysis of a diode side-primped Nd:YAG laser with a diffusive reflector (난반사체를 이용한 다이오드 횡여기 Nd:YAG 레이저의 최적화 설계 및 분석)

  • 이성만;윤미정;김선국;김현수;차병헌;문희종
    • Korean Journal of Optics and Photonics
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    • v.12 no.6
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    • pp.489-495
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    • 2001
  • We developed a design code for a diode side-pumped Nd:YAG laser with a diffusive reflector to investigate the optimum design conditions resulting in homogeneous absorption distribution and efficient laser output power. By including the thermal tensing effect in the calculation of the laser output power, the calculated output powers were in fairly good agreement with the experimental results within the stable resonator condition. The calculation method can be used effectively for a diode side-pumped Nd:YAG laser in choosing the optimum design parameters and in predicting the laser output power.

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Empirical Design Method for the Damping Force Characteristics of Shock Absorbers (쇽압쇼바 감쇠력 특성의 실험적 설계법 연구)

  • Baek, W.K.;Kim, C.M.
    • Journal of Power System Engineering
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    • v.15 no.4
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    • pp.11-18
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    • 2011
  • A Shock absorber is one of the most important components in vehicle suspension systems. In general, many repeated analyses are required for the design of a shock absorber to satisfy the suspension characteristics of a specific automobile, like fluid flow analysis and mechanical analysis. The purpose of this study is to develop a fast design tool for shock absorber designers. One of the efficient solutions for this can be an empirical design method considering phenomenological effects from the shock absorber design variables. In order to extract the shock absorber's experimental characteristics, we used Taguchi method. This method showed that which design variables have major effects for the shock absorber's damping characteristics. This empirical design method also showed the direction of the design changes to satisfy the designer's intension.

Energy-Efficient Scheduling with Individual Packet Delay Constraints and Non-Ideal Circuit Power

  • Yinghao, Jin;Jie, Xu;Ling, Qiu
    • Journal of Communications and Networks
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    • v.16 no.1
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    • pp.36-44
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    • 2014
  • Exploiting the energy-delay tradeoff for energy saving is critical for developing green wireless communication systems. In this paper, we investigate the delay-constrained energy-efficient packet transmission. We aim to minimize the energy consumption of multiple randomly arrived packets in an additive white Gaussian noise channel subject to individual packet delay constraints, by taking into account the practical on-off circuit power consumption at the transmitter. First, we consider the offline case, by assuming that the full packet arrival information is known a priori at the transmitter, and formulate the energy minimization problem as a non-convex optimization problem. By exploiting the specific problem structure, we propose an efficient scheduling algorithm to obtain the globally optimal solution. It is shown that the optimal solution consists of two types of scheduling intervals, namely "selected-off" and "always-on" intervals, which correspond to bits-per-joule energy efficiency maximization and "lazy scheduling" rate allocation, respectively. Next, we consider the practical online case where only causal packet arrival information is available. Inspired by the optimal offline solution, we propose a new online scheme. It is shown by simulations that the proposed online scheme has a comparable performance with the optimal offline one and outperforms the design without considering on-off circuit power as well as the other heuristically designed online schemes.

A Design of 16-bit Adiabatic Low-Power Microprocessor (단열회로를 이용한 16-bit 저전력 마이크로프로세서의 설계)

  • Shin, Young-Joon;Lee, Byung-Hoon;Lee, Chan-Ho;Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.31-38
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    • 2003
  • A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.

An Integrated Translation of Nuclear Power Plant Design Data ftom Specification-driven Plant Design Systems to a Neutral Product Model (사양 기반 플랜트 설계 시스템에서 생성된 원자력 플랜트 설계 데이터의 중립 모델로의 통합 변환)

  • Mun, Du-Hwan;Yang, Jeong-Sam;Han, Soon-Hung
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.2
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    • pp.96-104
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    • 2009
  • It gradually becomes important to study on how to efficiently integrate and manage plant lifecycle data such as 2D schematic and 3D solid data, logical configuration data, and equipment specifications data. From this point of view, converting plant design data from various systems into neutral data independent from any commercial systems is one of important technologies for the operation and management of plants which usually have a very long period of life. In order to achieve this goal, a neutral model for efficient integration and management of plant data was defined. After schema mapping between one of specification-driven plant design systems and the neutral model was performed, a plant data translator is also implemented according to the mapping result. Finally, by experiments with nuclear power plant design, the feasibility of the translator was demonstrated.

Conceptual model architecture design for power grid stabilization service using distributed resources (분산 자원을 활용한 전력망 안정화 서비스 개념적 모델 아키텍처 설계)

  • Jin Oh Kim;Young Min Kim;Joo Yeoun Lee
    • Journal of the Korean Society of Systems Engineering
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    • v.20 no.spc1
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    • pp.97-107
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    • 2024
  • Efforts to respond to climate change are being made in various ways around the world, and in the energy field, continuous research and pilot projects are underway through new and renewable energy, efficient power grid management, and power grid services. Systems are in place to realize these efforts, and the systems created allow for better effectiveness. When implementing a system, systems engineering methodology helps design a more systematic system and can provide verification accuracy and uniformity through intuitive connectivity. In this paper, the original requirements of the power grid stabilization system and the architecture of the system's essential constraints are constructed as a conceptual model and the boundaries and flows between components are defined. By utilizing distributed resources such as EV(Electric Vehicle) and ESS(Energy Storage System) in the power service platform system, we plan to design and build a next-generation power service system that can participate in the power stabilization market and implement a system necessary to respond to climate change in the future.

Design of Bit-Pattern Specialized Adder for Constant Multiplication (고정계수 곱셈을 위한 비트패턴 전용덧셈기 설계)

  • Cho, Kyung-Ju;Kim, Yong-Eun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.11
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    • pp.2039-2044
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    • 2008
  • The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

A Memory-efficient Hand Segmentation Architecture for Hand Gesture Recognition in Low-power Mobile Devices

  • Choi, Sungpill;Park, Seongwook;Yoo, Hoi-Jun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.473-482
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    • 2017
  • Hand gesture recognition is regarded as new Human Computer Interaction (HCI) technologies for the next generation of mobile devices. Previous hand gesture implementation requires a large memory and computation power for hand segmentation, which fails to give real-time interaction with mobile devices to users. Therefore, in this paper, we presents a low latency and memory-efficient hand segmentation architecture for natural hand gesture recognition. To obtain both high memory-efficiency and low latency, we propose a streaming hand contour tracing unit and a fast contour filling unit. As a result, it achieves 7.14 ms latency with only 34.8 KB on-chip memory, which are 1.65 times less latency and 1.68 times less on-chip memory, respectively, compare to the best-in-class.