• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.241-245
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• 1988

This paper reports the experiments regarding to diagnosis techniques for power transformers by measuring dissipation factor and moisture contents of mineral oils. Thermal aging environments of mineral oils were varied by the specially designed systems. Thermal aging of elevated temperature of $90^{\circ}C$ was performed for about 240 and 460 hours, respectively. Dissipation factor, permittivity, and water content were measured. Our test samples were not exposed to air. Dissipation factor increased while permittivity did not change. The level of dissipation factor determining the insulating quality of mineral oil was compared with the previous results of resistivity and several correction factor.

• Journal of Information Display
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• v.13 no.1
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• pp.1-6
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• 2012

Decreasing the thermal resistance is the critical issue for high-brightness light-emitting diodes. In this paper, the effects of some design factors, such as chip size (24 and 35 mil), substrate material (AlN and high-temperature co-fired ceramic), and die-attach material (Ag epoxy and PbSn solder), on the thermal-dissipation characteristics were investigated. Using the thermal transient method, the temperature sensitivity parameter, $R_{th}$ (thermal resistance), and junction temperature were estimated. The 35-mil chip showed better thermal dissipation, leading to lower thermal resistance and lower junction temperature, owing to its smaller heat source density compared with that of the 24-mil chip. By adopting an AlN substrate and a PbSn solder, which have higher thermal conductivity, the thermal resistance of the 24-mil chip can be decreased and can be made the same as that of the 35-mil chip.

• Journal of computational fluids engineering
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• v.11 no.2 s.33
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• pp.32-39
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• 2006

A heat dissipation modeling method of EEE parts is developed for thermal design and analysis of an satellite electronic equipment. The power consumption measurement value of each functional breadboard is used for the heat dissipation modeling method. For the purpose of conduction heat transfer modeling of EEE parts, surface heat model using very thin ignorable thermal plates is considered instead of conventional lumped capacity nodes. These modeling methods are applied to the thermal design and analysis of CTU EM and EQM and verified by thermal cycling and vacuum tests.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.29 no.4 s.235
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• pp.526-536
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• 2005

A heat dissipation modeling method of EEE parts, or semi-empirical heat dissipation method, is developed for thermal design and analysis an electronic equipment of geostationary satellite. The power consumption measurement value of each functional breadboard is used for the heat dissipation modeling method. For the purpose of conduction heat transfer modeling of EEE parts, surface heat model using very thin ignorable thermal plates is developed instead of conventional lumped capacity nodes. The thermal plates are projected to the printed circuit board and can be modeled and modified easily by numerically preprocessing programs according to design changes. These modeling methods are applied to the thermal design and analysis of CTU (Command and Telemetry Unit) and verified by thermal cycling and vacuum tests.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.3
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• pp.63-69
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• 2022

Compressor efficiency must be improved to reduce refrigerator power consumption. In this study, the heat dissipation rate through the compressor housing is increased via gap flow passages between the compressor body and housing. Four types of gap flow passages are considered for achieving the maximum heat-dissipation rate. In addition, thermal analysis is performed to examine the effect of increased heat dissipation rate on the energy efficiency ratio (EER). The results show that the heat dissipation rate, compressor superheat, and compressor EER increased by up to approximately 52%, 3 ℃, and approximately 1%, respectively.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.2
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• pp.150-157
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• 2014

Li-Ion battery is used in the most satellites now due to advantages such as weight, thermal dissipation and self discharge compared to the previous generations of electrochemical batteries. The performance analysis model of the Li-Ion battery is needed to aid the design of new satellite electrical power subsystem. This paper develops the performance analysis model of the Li-Ion battery to apply to the electrical power subsystem design and energy balance analysis on geostationary orbit. The analysis model receives the satellite bus power, solar array power and battery temperature and gives the battery voltage, charge and discharge currents, taper index, state of charge and power dissipation. The results from the performance analysis are compared and analyzed with the flight data to verify the model. The compared results show satisfactory without significant difference with the flight data.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.272-275
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• 2000

We investigated a resistive superconducting fault current limiter (SFCL) fabricated using YBCO thin films on 2-inch diameter sapphire substrates. Nearly identical SFCL units were prepared and tested. The units were connected in series and parallel to increase the current and voltage ratings. A serial connection of the units showed significantly unbalanced power dissipation between the units. This imbalance was removed by introducing a shunt resistor to the firstly quenched unit. Parallel connection of the units increased the current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current 25 Ap, was produced and successfully tested at a 220 V circuit. From the resistance increase, we estimated that the film temperature increases to 200 K in 5 msec, and 300 K in 120 msec. Successive quenches revealed that this system is stable without degradation in the current limiting capability under such thermal shocks as quenches at 220 V.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.455-458
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• 2004

We present an efficient heuristic algorithm to reduce glitch power dissipation in combinational circuits. In this paper, the total number of glitches are reduced by replacing existing gates with functionally equivalent ones and by gate sizing which classified into three types and by buffer insertion which classified into two types. The proposed algorithm combines gate freezing, gate sizing. and buffer insertion into a single optimization process to maximize the glitch reduction. Our experimental results show an average of $67.8\%$ glitch reduction and $32.0\%$ power reduction by simultaneous gate freezing, gate sizing, and buffer insertion.