• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.4
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• pp.355-360
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• 2014

Recently, the use of LED is increasing. This paper presents the new package process of thermal compression bonding using metal layered LED chip for the high power LED device. Effective thermal dissipation, which is required in the high power LED device, is achieved by eutectic/flip chip bonding method using metal bond layer on a LED chip. In this study, the process condition for the LED eutectic die bonder system is proposed by using the analysis program, and some experimental results are compared with those obtained using a DST (Die Shear Tester) to illustrate the reliability of the proposed process condition. The cause of bonding failures in the proposed process is also investigated experimentally.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.143-149
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• 2018

It has become ever harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Therefore, circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime. However, such an approach excessively increases the size and power dissipation of a system. As the impact of reliability, new techniques in designing aging-resilient circuits are necessary to reduce the impact of the aging stresses on performance, power, and yield or to predict the failure of a system. Therefore, in this paper, a novel low power on-chip self-tuning circuit considering the aging effects has been proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1477-1486
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• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.826-831
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• 2009

In this paper, a high power RF amplifier module using AlN substrate of high thermal conductivity has been proposed. This RF amplifier module has the advantage of compact size and effective heat dissipation for the packaging of high power chip. To fabricate the thru-hole and scribing line on AlN substrate, the key parameters of $CO_2$ laser were experimented. And then, microstrip lines and spiral planar inductors were fabricated on an AlN substrate using the thin-film process. The fabricated microstrip lines on the AlN substrate has an attenuation value of 0.1 dB/mm up to 10 GHz. The fabricated spiral planar inductor has a high quality factor, a maximum of about 62 at 1 GHz for a 5.65 nH inductor. Packaging of a RF power amplifier was implemented on an AlN substrate with thru-hole. From the measured results, the gain is 24 dB from 13 to 15 GHz and the output power is 33.65 dBm(2.3 W).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.845-848
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• 2009

Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronics circuits. Theyare also caleed power devices or when used in integrated circuits, called power ICs. Some common power devices are the power diode, thyristor, power MOSFET and IGBT (insulated gate bipolar transistor). A power diode or MOSFET operates on similar principles to its low-power counterpart, but is able to carry a larger amount of current and typically is able to support a larger reverse-bias voltage in the off-state. Structural changes are often made in power devices to accommodate the higher current density, higher power dissipation and/or higher reverse breakdown voltage. The vast majority of the discrete (i.e non integrated) power devices are built using a vertical structure, whereas small-signal devices employ a lateral structure. With the vertical structure, the current rating of the device is proportional to its area, and the voltage blocking capability is achieved in the height of the die. With this structure, one of the connections of the device is located on the bottom of the semiconductor.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.3
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• pp.146-152
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• 2006

In order to analyze the characteristics of series arcs that could happen in poor connections of electrical facilities, we made an apparatus which is similar to actual situation. series arcs are generated between copper and copper, copper and bronze, copper and brass, bronze and bronze, and then oxidation growth and voltage waveform were measured. A very small vibration with constant movement is needed to grow oxidation initially, whereas oxidation growth proceeded without a vibration after a certain amount of time. At first, blue white flame was generated initially between copper and copper, and then yellow flame was generated. In case of contact between copper and copper, the length of oxidation growth was about 7.1[mm] in 90[min]. In case of contact between copper and brass, the length of oxidation growth was about 4.3[mm] in 90[min], When bronze is contacted with copper, the lengths of oxidation growth were about 1.4[mm] in 20[min] and 2.7[mm] in 40[min] respectively, and no more oxidation growth was shown after that. In case of contact between brass and brass, the length of oxidation growth was about 1.2[mm] in 90[min], so it was the smallest compared to other cases. When copper is contacted with copper, the current through the load was about 1.6[A] and the power dissipation increased from 19[W] to 31[W]. In case of oxidation growth between copper and brass, the voltage changed from 8.4[V] to 11[V]. However, the voltage drop and the power dissipation between copper and brass were small compared to oxidation growth between copper and copper. When series arcs were generated between bronze and copper, a peak was shown at the beginning of voltage increase, and 40[min] later, oxidation material was not grown any longer. When oxidation growth occurred, voltage waveform showed irregular waveforms with tiny ripples.

• Journal of computational fluids engineering
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• v.21 no.2
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• pp.12-24
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• 2016

The standard ${\kappa}-{\varepsilon}$ and realizable ${\kappa}-{\varepsilon}$ models are adopted to improve the prediction performance on the recirculating flow. In this paper, the backward facing step flows are used to assess the prediction performance of the recirculation zone. The model constants of turbulence model are obtained by the experimental results and they have a different value according to the flow. In the case of an isotropic flow situation, decaying of turbulent kinetic energy should follow a power law behavior. In accordance with the power law, the coefficients for the dissipation rate of turbulent kinetic energy are not universal. Also, the other coefficients as well as the dissipation coefficient are not constant. As a result, a suitable coefficients can be varied according to each of the flow. The changes of flow over the backward facing step in accordance with model constants of the ${\kappa}-{\varepsilon}$ models show that the reattachment length is dependent on the growth rate(${\lambda}$) and the ${\kappa}-{\varepsilon}$ models can be improved the prediction performance by changing the model constants about the recirculating flow. In addition, it was investigated for the curvature correction effect of the ${\kappa}-{\varepsilon}$ models in the recirculating flow. Overall, the curvature corrected ${\kappa}-{\varepsilon}$ models showed an excellent prediction performance.