• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.279-280
• /
• 2008

Accelerated aging tests were conducted under laboratory conditions on two generator stator bars. Electrical stress is applied in No. 1 model stator bar. Electrical and thermal stresses are applied in No. 2 model stator bar. As aging times increased from 0 to 4780h, diagnostic tests were performed on No. 1 and No. 2 model stator bars. Diagnostic tests included AC current, dissipation factor(tan$\delta$) and partial discharge magnitude. The ${\Delta}tan{\delta}$ and $\Deta$I of No. 1 and No. 2 model stator bars increased with increased in aging time.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.12
• /
• pp.41-47
• /
• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Proceedings of the KIEE Conference
• /
• summer
• /
• pp.1272-1274
• /
• 2004

Recently the PDP is the most remarkable media for a next generation display device. In this paper, we proposed the PDP dedicated DC-DC converter using a new soft switching method because the PDP has a lot of power dissipation so we need to develope. The proposed converter using one transformer has soft switching and a advantage to lower voltage stress in switch and also is predicted to have high power efficiency. we proposed the principles and theory using the zero voltage switching and verified the validity through a experiment.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.890-893
• /
• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• Journal of the Korean Society of Industry Convergence
• /
• v.20 no.2
• /
• pp.187-194
• /
• 2017

This study examined the validity and reliability of the thermal safety design, in order to maintain the heat generated from integrated circuit (IC) chips in the converter, condenser, resistor, and transistor (which are considered as heat sources for thermoelectric devices with a printed circuit board) below target levels during the process of developing a control board and a main power board. The study analyzed the heat generation and dissipation characteristics of the entire printed circuit board (PCB) model to examine its thermal safety.

• Journal of Power Electronics
• /
• v.19 no.1
• /
• pp.296-306
• /
• 2019

The flyback topology is being widely used in power adapters. The coupling capacitance between primary and secondary windings of a flyback transformer is the main path for common-mode (CM) noise conduction. A Y-cap is usually used to effectively suppress EMI noise. However, this results in problems in space, cost, and the danger of safety leakage current. In this paper, the CM noise behaviors due to the electric field coupling of the transformer windings in a flyback adapter with synchronous rectification are analyzed. Then a scheme with balance winding is proposed to reduce the CM noise with a transformer winding design that eliminates the Y-cap. The planar transformer has advantages in terms of its low profile, good heat dissipation and good stray parameter consistency. Based on the proposed scheme, with the help of a full-wave simulation tool, the key parameter influences of the transformer PCB winding design on CM noise are further analyzed. Finally, a PCB transformer for an 18W adapter is designed and tested to verify the effectiveness of the balance winding scheme.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.6
• /
• pp.853-856
• /
• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.2
• /
• pp.351-356
• /
• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.438-445
• /
• 2017

This paper presents a low-power high-resolution band-pass ${\Sigma}{\Delta}$ ADC for accelerometer applications. The proposed band-pass ${\Sigma}{\Delta}$ ADC consists of a high-performance 6-th order feed-forward ${\Sigma}{\Delta}$ modulator with 1-bit quantization and a low-power, area-efficient digital filter. The ADC is fabricated in 180 nm 1P6M mixed-signal CMOS process with a die area of $5mm^2$. This high-resolution ADC got 90 dB peak signal to noise plus distortion ratio (SNDR) and 96 dB dynamic range (DR) over 4 kHz bandwidth, while the intermediate frequency (IF) is shifting from 100 KHz to 200 KHz. The power dissipation of the chip is 5.6 mW under 1.8 V (digital)/3.3 V (analog) power supply.

• Proceedings of the KIEE Conference
• /
• 2002.07a
• /
• pp.336-338
• /
• 2002

We improved quench properties of a superconducting fault current limiter (SFCL) based on YBCO thin films by their serial and parallel combinations. The SFCL consisted of 6 switching elements fabricated of 4 inch-diameter YBCO thin films. Simple serial connection resulted in imbalanced power dissipation between switching elements even at the quench current difference of 0.6A. On the other hand, $2{\times}2\;and\;3{\times}2$ stack combinations produced simultaneous quenches. The $3{\times}2$ stack combination showed better simultaneous quench behavior than the $2{\times}2$ stacks. This is suggested to be because the currents between switching elements in parallel connection of the $3{\times}2$ stacks were more effectively redistributed than the $2{\times}2$ stacks.