• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.856-859
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• 2002

This paper proposes a high-performance VLSl architecture using distributed arithmetic for higher-order FIR filters with complex coefficients. For the purpose of realizing high sampling rate with small latency in high-order filters, we apply distributed arithmetic[1］. Moreover, in order to decrease drastically the power dissipation, the structure applying not ROM's but optimum function circuits which we have previously proposed, is utilized［2]［3］. However, this structure increases in the number of adders as compared to the conventional structure applying ROM's. In order to realize a more effective method for further higher-order filter, we propose newly an implementation applying two methods which have large effects on the unit using the adders. First , we propose an implementation applying SFAs(Serial Full Adders) and SFSs(Serial Full Subtractors). Second, we propose a structure applying proposed 4-2 adders. Finally, it is shown that the proposed architecture is an effective way to realize low power dissipation and small latency while the sampling rate is kept constant for further higher-order filters with complex coefficients.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.4
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• pp.309-314
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• 2012

To assess the condition of stator insulation, nondestructive and overpotential tests were performed on four high voltage motors. The stator windings under these tests have nominal ratings of 6.6 kV. After completing nondestructive tests, the AC overvoltage applied to the stator windings was gradually increasing until insulation failure in order to obtain the breakdown voltage. No. 1, No. 2, No. 3 and No. 4 of 6.6 kV motors failed near rated voltage of 18.4 kV, 19.8 kV, 19.7 kV and 21.7 kV, respectively. The breakdown voltage of four motors was higher that expected for good quality coils(14.2 kV) in 6.6 kV motors. Almost all of failures were located in a line-end coil at the exit from the core slot. The breakdown voltages and the types of defects showed strong relation to the stator insulation tests such as in the case of AC current, dissipation factor($tan{\delta}$) and partial discharge magnitude.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.338-340
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• 2017

Breakdown of solid insulating materials in power equipment could result in undesired outages and replacements, and may be due to an increase in electric stress on the material. Therefore, it is necessary to conduct a proper diagnosis of materials before their practical use. In this work, a few inherent properties of different non-cellulosic insulating materials, such as Nomex, Teflon, laminated Nomex, glass bonded mica, epoxy resin bonded mica paper, and epoxy resin bonded fiberglass, have been evaluated by performing non-destructive dielectric diagnostic measurements, and an attempt has been made to correlate these basic parameters to evaluate the breakdown strength (BDS). An equation has been proposed using a basic theory which defines the correlation between the BDS, dielectric constant, dissipation factor, sample thickness, and volume resistivity. The results obtained from the equation are also compared with the experimental values. The suggested equation will be helpful to predict the BDS of any non-cellulosic material without experimentation in the laboratory.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.6
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• pp.42-50
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• 2006

This paper addresses the optimized thermal modeling methodology for spacecraft board level thermal analysis. A direct thermal modeling of external and internal structure of active parts which have high power dissipation is newly proposed, based on conventional plate modeling for Printed Circuit Board(PCB). The parts thermal modeling results were compared with other generic methodologies and verified by thermal vacuum test. This parts thermal modeling was directly applied to thermal analysis of CS(Communication Subsystem) board of HAUSAT-2 small satellite. As a result, it was confirmed that the parts thermal modeling can complement other conventional modeling methodologies. A parts thermal modeling is very effective for thermal control design, since the existing thermal problems can be solved at the parts level in advance.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.10a
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• pp.231-234
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• 2005

The high temperature deformation behavior of AZ 31 Mg alloy was investigated by designing a back propagation neural network that uses a gradient descent-learning algorithm. A neural network modeling is an intelligent technique that can solve non-linear and complex problems by learning from the samples. Therefore, some experimental data have been firstly obtained from continuous compression tests performed on a thermo-mechanical simulator over a range of temperatures $(250-500^{\circ}C)$ with strain rates of $0.0001-100s^{-1}$ and true strains of 0.1 to 0.6. The inputs for neural network model are strain, strain rate, and temperature and the output is flow stress. It was found that the trained model could well predict the flow stress for some experimental data that have not been used in the training. Workability of a material can be evaluated by means of power dissipation map with respect to strain, strain rate and temperature. Power dissipation map was constructed using the flow stress predicted from the neural network model at finer Intervals of strain, strain rates and subsequently processing maps were developed for hot working processes for AZ 31 Mg alloy. The safe domains of hot working of AZ 31 Mg alloy were identified and validated through microstructural investigations.

• Steel and Composite Structures
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• v.14 no.6
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• pp.587-604
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• 2013

There are few technical documents regulated structural performance and engineering criteria in domestic market for Structural insulated panels in Korea. This paper was focused to identify fundamental performance under monotonic loading and cyclic loading for SIPs in shear wall application. Load-displacement responses of total twelve test specimens were recorded based on shear stiffness, strength, ultimate load and displacement. Finally energy dissipation of each specimen was analyzed respectively. Monotonic test results showed that ultimate load was 44.3 kN, allowable shear load was 6.1 kN/m, shear stiffness was 1.2 MN/m, and ductility ratio was 3.6. Cyclic test was conducted by two kinds of specimens: single panel and double panels. Cyclic loading results, which were equivalent to monotonic loading results, showed that ultimate load was 45.4 kN, allowable shear load was 6.3 kN/m. Furthermore the accumulated energy dissipation capability for double panels was as 2.3 times as that for single panel. Based on results of structural performance test, it was recommended that the allowable shear load for panels should be 6.1 kN/m at least.

• Journal of Sensor Science and Technology
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• v.22 no.4
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• pp.268-275
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• 2013

Efficient energy management becomes a critical design issue for complex WSN (Wireless Sensor Network). Most of complex WSN employ the sleep mode to reduce the energy dissipation. However, it should cause the reduction of sensing coverage. This paper presents new wake-up algorithm for reducing energy consumption in complex WSN. The proposed wake-up algorithm is devised using geometric probability. It determined which node will be waked-up among the nodes having overlapped sensing coverage. The only one sensor node will be waked-up and it is ready to sense the event occurred uniformly. The simulation results show that the lifetime is increased by 15% and the sensing coverage is increased by 20% compared to the other scheduling methods. Consequently, the proposed wake-up algorithm can eliminate the power dissipation in the overlapped sensing coverage. Thus, it can be applicable for the various WSN suffering from the limited power supply.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.