• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.229-232
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• 2001

Modified Materka-Kacprzak 대신호 MESFET(Metal Semiconductor Field Effect Transistor) model을 사용하여 4H-SiC MESFET의 대신호 모델링을 수행하였다. Silvaco사의 소자 시뮬레이터인 ATLAS를 사용하여 4H-SiC MESFET 소자 시뮬레이션을 수행하고, 이 절과를 modified Materka 대신호 모델을 사용하여 모델링 하였다. 시뮬레이션 및 모델링 결과는 -8V의 pinch off 전압과 V/sub GS=0V, V/sub DS=25V에서 I/sub DSS=270㎃/㎜, G/sub m=45㎳/㎜를 얻을 수 있었고, 진력 특성 시뮬레이션을 통해 2㎓, V/sub GS=-4V, V/sub DS=25V에서 1()dB의 Gain과 34dBm(1dB compression point)의 출력전력, 7.6W/㎜의 전력밀도, 37%의 PAE(power added efficiency)를 얻을 수 있었다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.118-121
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• 2003

A new approach, using MEMS, for improving the performance of high efficiency amplifiers is proposed in this paper. The MEMS tuning element is described as a variable-length shorted CPW stub. Class-E amplifiers can be optimally tuned by these MEMS tuning elements because their operation varies with the impedance of the output tuning circuit. A MEMS tuning element was simulated using full-wave EM simulators to obtain its S-parameters. A Class-E amplifier with the MEMS was designed at 8GHz. The non-linear operation of this amplifier was simulated to explore the effect of the MEMS tuning. Comparing the initially designed amplifier without MEMS, the Power Added Efficiency (PAE) of the amplifier with MEMS is improved from 46.3% to 66.9%. For the amplifier with MEMS, the nonlinear simulation results are PAE = 66.90%, $\eta$(drain efficiency) = 75.89%, and $P_{out}$ = 23.37 dBm at 8 GHz. In this paper, the concept of the MEMS tuning element is successfully applied to the Class E amplifier designed with transmission lines.

• 전기전자학회논문지
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• 제20권3호
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

• ETRI Journal
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• 제39권5호
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• pp.737-745
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• 2017

A 6-GHz-to-18-GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a $0.25-{\mu}m$ AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power-added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse-mode condition of a $100-{\mu}s$ pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.113-117
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• 2003

This paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard $0.25{\mu}m$ CMOS technology and is shown to deliver 100mW output power to load with 41% power added efficiency(PAE) from a 2.5V supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.335-339
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• 2003

This Paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard 0.25$\mu\textrm{m}$ CMOS technology and is shown to deliver 100mW output Power to load with 41％ power added efficiency(PAE) from a 2.5V supply.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.87-90
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• 2005

High-efficiency switched-mode circuits such as the class-E amplifier are well-known in the MHz frequency range. The class-E amplifier is a type of switching mode amplifier offering very high efficiency approaching 100%. In this paper of the class-E amplifier by using pHEMT device, the design has been done theoretically and experimentally, with simulation by using the harmonic balance method using circuit simulator. The amplifier using microstrip circuit and the pHEMT demonstrate 66% power-added- efficiency (PAE) at 2.4GHz with 17.6dBm of output power.

• 한국전자파학회논문지
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• 제26권9호
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• pp.783-789
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• 2015

본 논문에서는 long term evolution(LTE) 통신을 위한 2.6 GHz 대역에서 동작하는 고효율 Doherty 전력증폭기를 설계하였다. 2차 및 3차 고조파 임피던스를 조정하기 위한 간단한 구조의 정합 네트워크를 통해 전력증폭기의 고효율 동작을 달성하였다. Doherty 전력증폭기는 다양한 측면에서 장점을 갖는 GaN-HEMT 소자를 이용하여 제작되었으며, 10 MHz의 대역폭 및 6.5 dB 첨두 전력 대 평균 전력비(PAPR)의 특성을 갖는 LTE downlink 신호를 이용하여 측정되었다. 평균 전력 33.4 dBm에서 13.1 dB의 전력 이득, 57.6 %의 전력부가효율(PAE) 및 -25.7 dBc의 인접채널누설비(ACLR) 특성을 갖는다.

• Journal of electromagnetic engineering and science
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• 제14권1호
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• pp.1-8
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• 2014

A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 ${\mu}m$ RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the $2^{nd}$ harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an $ACLR_{E-UTRA}$ of -32.7 dBc at an average output power of 27 dBm.

• 대한전자공학회논문지TC
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• 제48권2호
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• pp.85-89
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• 2011

본 논문에서는 메타구조를 이용하여 하나의 RF LDMOS로 새로운 Class-E 전력증폭기를 구현하였다. CRLH 구조는 Class-E 전력증폭기 특성을 갖는 메타물질 전송 선로를 만들 수 있다. CRLH 전송 선로는 전력증폭기의 정합 회로를 구현을 위하여 주파수 오프셋과 CRLH 전송 선로의 비선형 위상 기울기에 의해 얻을 수 있다. 또한, 제안된 전력증폭기의 효율을 향상 시키기 위하여 출력 정합 회로에 CRLH 구조를 이용하여 구현하였다. 동작 주파수는 13.56MHz로 정하였다. Class-E 전력 증폭기의 측정된 출력 전력은 39.83dBm, 이득은 11.83 dB이다. 이 지점에서 얻은 전력효율(PAE)은 73%이다.