• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.11
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• pp.981-987
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• 2014

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a MOSFET (metal-oxide semiconductor field effect transistor), a PWM-IC (pulse width modulation-integrated circuit) controller, inductor, capacitor, etc. It is shown that the variation of threshold voltage and the breakdown voltage in the electrical characteristics of MOSFET occurs by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 5 heavy ions make the gate of MOSFET broken in SEGR (Single Event Gate Rupture) testing. TID testing on MOSFET is accomplished up to the total dose of 40 krad, and the cross section($cm^2$) versus LET(MeV/mg/$cm^2$) in the MOSFET operation is studied at SEGR testing after implementation of the controller board.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1152-1155
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• 1995

An analytic model for the optimum design of the power MOSFET considering the degradation of the breakdown voltage by the three dimensional effect is proposed. The proposed method gives the optimum design parameters such as the lateral radius of window curvature and the doping concentration of the epi-layer, which does not minimize the on-resistance but also maintains the required breakdown voltage. The analytical results are verified by the quasi 3D simulation tools, MEDICI, and it is found that the proposed method may be a good guideline for the design of power MOSFET.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.190-191
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• 2013

본 논문에서는 기존의 Si MOSFET을 사용한 전력시스템과 비교하여 WBG(Wide Band Gap)특성을 갖는 GaN(Gallium Nitride) FET을 사용한 전력시스템을 비교 분석한다. 대표성을 갖는 평가가 가능하도록 가장 일반적인 FB 구조를 대상으로 Si MOSFET과 GaN FET을 각각 적용하고, 다양한 기준 조건에서 효율과 전력 밀도 등 성능을 비교한다. 전체 과정은 수학적 계산 및 시뮬레이션으로 검증한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.359-359
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• 2010

IGBT(Insulated Gate Bipolar Transistor) 란 MOS(Metal Oxide Silicon) 와 Bipolar 기술의 결정체로 낮은 순방향 손실(Low Saturation)과 빠른 Speed를 특징으로 기존의 Thyristor, BJT, MOSFET 등으로 실현 불가능한 분양의 응용처를 대상으로 적용이 확대 되고 있고, 300V 이상의 High Power Application 영역에서 널리 사용되고 있는 고효율, 고속의 전력 시스템에 있어서 필수적으로 이용되는 Power Device이다. IGBT는 출력 특성 면에서 Bipolar Transistor 이상의 전류 능력을 가지고 있고 입력 특성 면에서 MOSFET과 같이 Gate 구동 특성을 갖기 때문에 High Switching, High Power에 적용이 가능한 소자이다. 반면에, Conventional IGBT는 MOSFET과 달리 IGBT 내부에 Anti-Parallel Diode가 없기 때문에 Inductive Load Application 적용시에는 별도의 Free Wheeling Diode가 필요하다. 그래서, 본 논문에서 별도의 Anti-Parallel Diode의 추가 없이도 Inductive Load Application에 적용 가능한 RC IGBT를 적용하여 600V/15A급 Three Phase Inverter Module을 제안 하고자 한다.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.713-718
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• 1998

Due to high power ratings and low conduction loss, the IGBT has become more attractive in high power applications. However, its slower characteristics than those of MOSFET cause severe switching losses and switching frequency limitation. This paper proposes the IGBT's soft switching concept with the help of MOSFET, where each of the IGBT and MOSFET plays its role during on-periods and switching instants. Also, the switching losses are analyzed by using the linearized modeling and the modeling and the operations of a converter are investigated to confirm the soft switching of IGBT's.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1451-1453
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• 1994

A monolithic current limiting power MOSFET, which may be easily fabricated by the conventional DMOS process, is proposed. The proposed current limiting MOSFET consists of main power cells, sensing cells, and NPN lateral bipolar transistor so that users can adjust the current limiting levels with only one external resistor. The behaviors of the proposed device are numerically simulated and analyzed by 2-D device simulator MEDICI and mixed-mode simulator CA-AAM(Circuit Analysis Advanced Application Module).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.470-473
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased patting density. The devices are scaled down day by day. Therefore, This paper investigates how MOSFET structures influence on transport properties in according to change of channel length and bias and, observes impact ionization between the drain and the gate. This paper proposes three models, i.e., conventional MOSFET, LDD MOSFET and EPI MOSFET. The gate lengths are 0.3$\mu\textrm{m}$ 0.15$\mu\textrm{m}$, 0.075$\mu\textrm{m}$ and scaling factor is λ = 2. We have presented MOSFET's characteristics such as I-V characteristic, impart ionization, electric field, using the TCAD. We have analyzed the adaptive channel and doping influences

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.110-113
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• 1993

The MOSFET synchronous rectification in the Active-Clamp Forward converter is presented. The Active-Clamp Forward converter has little dead time during the off time of the main switch and it is suitable for the MOSFET synchronous rectification comparing to the other Forward converter topologics. Using the MOSFET synchronous rectification on the Active-Clamp Forward converter with 3.3[V] output and 500[kHz] switching frequency, the improvement of efficiency is achieved comparing with the conventional Schottky barrier diode rectification.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.2
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• pp.235-238
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• 2008

This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.