• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.265-266
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• 2016

본 논문에서는 EV와 NEV 겸용 모듈형 급속충전기를 위한 10kW급 3레벨 DC-DC 컨버터를 제안한다. 제안한 컨버터는 600V 정격의 MosFET로 고속스위칭을 위하여 3레벨 컨버터를 채용하였고 순환전류를 최소화하기 위하여 커플인덕터를 적용한 듀티제어방식의 풀브릿지 컨버터로서 스위치의 ZVS 턴 온과 다이오드의 ZCS 턴 오프를 성취하였다. 또한 EV(200~500V)와 NEV(50~100V)의 넓은 충전전압 범위에서 고효율을 달성하기 위해 하이브리드 스위칭기법을 적용하였다. 10kW 시작품 개발을 통해 정격부하 효율 97.32%, 최고효율 97.43%를 달성하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.46-52
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• 1991

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.815-818
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• 1998

The Insulated Gate Bipolar Transistor has the characteristics of MOSFET and BJT. The characteristics of proposed device exhibit high speed switching, the voltage controlled property, and the low ON resistance. This hybrid device has been used and developed continuously in the power electronic engineering field. We can simulate many IGBT circuits, such as the motor drive circuit, the switching circuits etc, with PSpice. However, some problems in PSpice is that the IGBT is old-fashioned and is very difficult to get it. In this paper, the IGBT in PSpice is considered as the basic structure. We changed the valuse of base width, gate-drain overlaping area, device area, and doping concentration, then calculated MOS transconductance, ambipolar recombination lifetime etc. Using this resultant parameter, we could predict the transient response characteristicsof IGBT, for examplex, voltage overshoot, the rising curve of voltage, and the falling curve of current.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.799-805
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• 2004

Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating $N^+$ emitter indicates to have the better characteristics of latch-up current and breakover voltage.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.559-560
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• 2008

In this paper, I proposed 10bits 40MS/s Pipelined A/D converter. The op-amps for SHA and MDAC designed folded-cascode amplifier with gain-booster. And the MOS transistors with a low threshold voltage are employed to low on-resistor and parasitic capacitance. The power dissipation is 119㎽ at 1.2V and 40MS/s

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.571-572
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• 2008

We propose a 4-bit 1.6GSample/s flash-A/D converter realized in a digital 0.18um 1-poly 4-metal CMOS technology. To achieve low power with good performance, we employ immanent C2MOS comparator scheme. The kickback noise is one of the most important issue in A/D comparator performance. To decrease the effect of kickback noise, here we introduce kickback neutralization technique. The designed A/D converter has an effective number of bits(ENOBs) of 3.93 while using 32mW operating at 1.6GHz.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.759-762
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• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.51-54
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• 2000

This paper presents an efficient method for estimating maximum simultaneous switching noise(SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use ａ-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions. Our method predicts the maximum SSN values more accurately as compared to existing approaches even in more practical cases such that there exist some of output drivers not in transition.