• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.94-94
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• 1996

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.166-166
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• 2008

• Proceedings of the Materials Research Society of Korea Conference
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• 2001.11a
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• pp.158-158
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• 2001

• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.123-129
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• 2003

Thin transparent Cu films in the thickness range of 10 ~ 40 nm are deposited by rf-magnetron sputtering on porous silicon (PS) anodized on p-type silicon in dark. Microstructural features of the Cu films are investigated using SEM, AFM and XRD techniques. The RMS roughness of the Cu films is found to be around 1.47 nm and the grain growth is columnar with a (111) preferred orientation and follows the Volmer-Weber mode. The photoluminescence studies showed that a broad luminiscence peak of PS near the blue-green region gets blue shifted (~0.05 eV) with a small reduction in intensity and therefore, Cu-related PL quenching is absent. The FTIR absorption spectra on the PS/Cu structure revealed no major change of the native PS peaks but only a reduction in the relative intensity. The I-V characteristic curves further establish the Schottky nature of the diode with an ideality factor of 2.77 and a barrier height of 0.678 eV. An electroluminiscence (EL) signal of small intensity could be detected for the above diode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.285-289
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• 2003

This paper proposes a 10 ${\mu}{\textrm}{m}$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and rnicrornachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation (50$0^{\circ}C$, 1 hr at $H_2O$/O$_2$) and rapid thermal oxidation (RTO) process (105$0^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to 10 ${\mu}{\textrm}{m}$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 1 dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about - 20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• Journal of Sensor Science and Technology
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• v.5 no.5
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• pp.21-29
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• 1996

A piezoresistive silicon acceleration sensor with 8 beams, utilized by an unique silicon micromachining technique using porous silicon etching method which was fabricated on the selectively diffused (111)-oriented $n/n^{+}/n$ silicon subtrates. The width, length, and thickness of the beam was $100\;{\mu}m$, $500\;{\mu}m$, and $7\;{\mu}m$, respectively, and the diameter of the mass paddle (the region suspended by the eight beams) was 1.4 mm. The seismic mass on the mass paddle was formed about 2 mg so as to measure accelerations of the range of 50g for automotive applications. For the formation of the mass, the solder mass was loaded on the mass paddle by dispensing Pb/Sn/Ag solder paste. After the solder paste is deposited, Heat treatment was carried out on the 3-zone reflow equipment. The decay time of the output signal to impulse excitation of the fabricated sensor was observed for approximately 30 ms. The sensitivity measured through summing circuit was 2.9 mV/g and the nonlinearity of the sensor was less than 2% of the full scale output. The output deviation of each bridge was ${\pm}4%$. The cross-axis sensitivity was within 4% and the resonant frequency was found to be 2.15 KHz from the FEM simulation results.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1825-1828
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• 2008

A simple method for the fabrication of porous nano-master for antireflective surface is presented. In conventional fabrication methods for antireflective surface, coating method with low refractive index has usually been used. However, it is required to have high cost and long times for mass production. In this paper, we suggested the fabrication method of antireflective surface by the hot embossing process using the porous nano patterned master on silicon wafer fabricated by low-temperature anodic aluminum oxidation. Through multi-AAO and etching processes, nano patterned master with high aspect ratio was fabricated at the large area. Pore diameter and inter-pore distance are about 150nm and from 150 to 200nm. In order to replicate anti-reflective structure, hot embossing process was performed by varying the processing parameters such as temperature, pressure and embossing time etc. Finally, antireflective surface can be successfully obtained after etching process to remove selectively silicon layer of AAO master.

• Journal of Integrative Natural Science
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• v.2 no.1
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• pp.41-44
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• 2009

Photonic crystals containing multiple rugate structure are prepared by electrochemical etchings. Typically etched rugate PSi prepared in this study. Etching is carried out in a Teflon cell by using a two-electrode configuration with a Pt mesh counter electrode. They exhibit sharp photonic band gaps in the optical reflectivity spectrum. This reflectivity can be tuned to appear anywhere in the visible to near-infrared spectral range, depending on the programmed etch waveform. We study the method of full width half maxima and reflectivity index control by using amplitude.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.92-97
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• 2002

We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900 ^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^2$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.