• 제목/요약/키워드: polysilicon

검색결과 324건 처리시간 0.024초

다결정 실리콘 Self-align에 의한 바이폴라 트랜지스터의 제작

  • Chae, Sang-Hun;Gu, Jin-Geun;Kim, Jae-Ryeon;Lee, Jin-Hyo
    • ETRI Journal
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    • 제7권4호
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    • pp.11-14
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    • 1985
  • A polysilicon self-aligned bipolar n-p-n transistor structure is described, which can be used in high speed and high packing density LSI circuits The emitter of this transistor is separated less than $0.4\mum$ with base contact by polysilicon self-align technology. Through all the process, the active region of this device is not damaged. therefore a high performance device is obtained. Using the transistor with $3.0\mum$ design rules, a CML ring oscillator has per-gate minimum propagation delay time of 400 ps at 2.7 mW power consumption condition.

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Hot-Carrier Effects of $BF_2$ Ion-Implanted Surface-Channel LDD PMOSFET ($BF_2$ 이온 주입한 표면 채널 LDD PMOSFET의 Hot-Carrier 효과)

  • 양광선;박훈수;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • 제28A권12호
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    • pp.53-58
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    • 1991
  • Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

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Characterization of Pt Bottom Electrode Deposited on Sputtered-Ru/polysilicon by Metalorganic Chemical Vapor Deposition (유기금속 화학증착법에 의해 Sputtered-Ru/Polysilicon 위에 증착된 Pt 전극의 특성)

  • Choe, Eun-Seok;Yang, Jeong-Hwan;Yun, Sun-Gil
    • Korean Journal of Materials Research
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    • 제9권4호
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    • pp.368-372
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    • 1999
  • The suggested electrode structure of MOCVD-Pt/sputtered-Ru/polysilicon has an excellent adhesion with increasing annealing temperatures and shows a stable electrode structure up to $600^{\circ}C$. However, the ruthenium used for barrier layer increased the roughness of platinum bottom electrodes because ruthenium diffused through the Pt bottom electrode and reacted with oxygen during the annealing above $700^{\circ}C$. The surface roughness increased the resistivity of Pt bottom electrodes. The resistivity of samples annealed at $600^{\circ}C$ was about $13\mu$Ω.cm. The electrode structure was possible to apply for ferroelectric thin film integration of semiconductor memory devices.

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Design, Microfabricaiton and Testing of Laterally-Resonating Polysilicon Microactuators (수평공진형 다결정실리콘 미소액추에이터의 설계, 제작 및 시험)

  • Jo, Yeong-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • 제20권5호
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    • pp.1363-1371
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    • 1996
  • This paper presents the design, fabrication, and testing of polysilicon electrostatic microactuators that resonate in the direction parallel to the silicon susbstrates. A set of six different designs has been developed using a theoretical model and design formulae developed for the mocroactuators. Microactuator prototypes are fabricated from a 2.1 $\mu{m}$-thick LPCVD polysilicon film, using a 4-mask surface-micromachining process. The prototypes are tested under a d.c. bias voltage of 45V with an a.c. drive voltage amplitude of 20 v.Measured resorant frequencies are in the ranges of 40-60 kHz, showing a good agreement to their theoretical estimates within error bounds of .$\pm$.5%. Important issues inthe design and microfabrication of the microactuators are discussed, together with potential applicaitons of the key technology involved.

A novel self-aligned offset gated polysilicon thin film transistor without an additional offset mask (오프셋 마스크를 이용하지 않는 새로운 자기 정합 폴리 실리콘 박막 트랜지스터)

  • 민병혁;박철민;한민구
    • Journal of the Korean Institute of Telematics and Electronics A
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    • 제32A권5호
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    • pp.54-59
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    • 1995
  • We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

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Comparison of Temperature Characteristics Between Single and Poly-crystalline Silicon Pressure Sensor (단결정 및 다결정 실리콘 압력센서의 온도특성 비교)

  • Park, Sung-June;Park, Se-Kwang
    • Proceedings of the KIEE Conference
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    • 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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    • pp.342-344
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    • 1995
  • Using piezoresistive effects of single-crystal and poly-crystalline silicon, pressure sensors of the same pattern were fabricated for comparison of temperature characteristics. Optimum size and aspect ratio of rectangular sensor diaphragm were calculated by FEM. For polsilicon pressure sensor, polysilicon resistors of Wheatstone bridge were deposited by LPCVD to be used in a wide' temperature range. Polysilicon pressure sensors showed more stable temperature characteristics than single-crysta1 silicon in the range of $-20\sim125[^{\circ}C]$. To get low TCO (Temperature Coefficient of Offset), below $\pm$3 [${\mu}V/V/^{\circ}C$], it is needed for each TCR of piezoresistors to have a deviation within $\pm25[ppm/^{\circ}C]$ less than $\pm500[ppm/^{\circ}C]$ of resistors for polysilicon pressure sensor can result in low TCS(Temperature Coefficient of Sensitivity) of -0.1[%FS/$^{\circ}C$].

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Fabrication and Testing of a Polysilicon Piezoresistive Accelerometer using p+ Silicon Diaphragm (p+ 실리콘 박막을 이용한 폴리실리콘 압저항 가속도계의 제작 및 측정)

  • Yang, E.H.;Jeong, O.C.;Yang, S.S.
    • Proceedings of the KIEE Conference
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    • 대한전기학회 1996년도 하계학술대회 논문집 C
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    • pp.1994-1996
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    • 1996
  • This paper presents the fabrication and testing of a polysilicon piezoresistive accelerometer with p+ silicon diaphragm by simple process such as two step photolithography for the RIE process to form the cantilevers and a deep anisotropic etch process for the complete fabrication of the accelerometer. The fabricated accelerometer consists of a seismic mass and four cantilevers on which polysilicon piezoresistors are formed. The measurement of the output signal from the bridge circuit of the fabricated accelerometer is carried out with the HP 3582A spectrum analyzer. The analysis of the experimental result is showed in terms of the sensitivity and the resonant frequency. At atmospheric condition, the measurement values of the sensitivity and the resonant frequency are $11\;{\mu}V/Vg$ and 475 Hz, respectively.

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A Polysilicon Capacitive Microaccelerometer with Unevenly Distributed Comb Electrodes (비등간격 수평감지 전극구조의 정전용량형 다결정 실리콘 가속도계)

  • Han, Ki-Ho;Cho, Young-Ho
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • 제50권7호
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    • pp.346-350
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    • 2001
  • We present a surface-micromachined polysilicon capacitive accelerometer using unevenly distributed comb electrodes. The unique features of the accelerometer include a perforated proof-mass and the inner and outer comb electrodes with uneven electrode gaps. The perforated proof-mass reduces stiction between the structure and the substrate and the unevenly distributed electrodes shorten the electrode length required for a given sensitivity. The polysilicon accelerometer has been fabricated by the conventional 6-mask surface-micromachining process and showes a sensitivity of 1.03mV/g with a hybrid detection circuitry.

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Stability Enhancement of Polysilicon Thin-Film Transistors with A Source-tied-to-body

  • Choi, B.D.;Choi, D.C.;Jung, J.Y.;Park, H.H.;Chung, H.K.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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    • pp.293-293
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    • 2005
  • The differences between floating and grounded body effects in polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated by making a body contact. The floating body effects such as kink effect, subthreshold slope change, and body current characteristics are explained and modeled by impact ionization, which causes source body turn on, and activates the parasitic bipolar junction transistors (BJTs). These effects become crucial for channel lengths of 4㎛ or shorter. Our data show that making a body contact reduces kink effects significantly and identifies impact ionization mechanism in polysilicon TFTs.

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Effects of Doping Concentration in Polysilicon Floating Gate on Programming Threshold Voltage of EEPROM Cell (EEPROM 셀에서 폴리실리콘 플로팅 게이트의 도핑 농도가 프로그래밍 문턱전압에 미치는 영향)

  • Chang, Sung-Keun;Kim, Youn-Jang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • 제20권2호
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    • pp.113-117
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    • 2007
  • We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.