• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.640-645
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• 1987

Surface states and interfacial phenomena at the undoped polycrystalline semiconductor particale-electrolyte interfaces were qualitatively analyzed based on the zeta potentials which were measured with microelectrophoresis measurements. The suspensions were composed of the undoped polycrystaline silicon(Si) or gallium arsenide (GaAs) semiconductor particles stalline Si and GaAs particles in the KCl electrolytes was 3.73~6.2x10**-4 cm\ulcornerV.sec and -2.3~1.4x10**-4cm\ulcornerV.sec at the same conditions, respectively. The range of zeta potentials corresponding to the electrophoretic mobilities is 47.8~80.1mV and -30.1~17.9mV, respectively. The variation of the zeta potentials of the undoped polycrystalline Si was similar to the doped crystalline Si. On the other hand, two points of zeta potential reversal occurred at the undoped polycrystalline GaAs-KCl electrolyte interfaces. The surface states of the undoped polycrystalline Si and GaAs were dominated by positively charged donor surface states. These surface states are attributed to adsorbed ion surface states (slow states) at the semiconductor oxide layer-electrolyte interfaces.

• Journal of the Korean institute of surface engineering
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• v.43 no.1
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• Korean Journal of Materials Research
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• v.18 no.10
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• pp.552-556
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• 2008

Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of $B_2H_6$. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1999.08a
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• pp.313-319
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• 1999

The development of deformation texture in FCC polycystalline metals during rolling was simulated by the finite element analysis using a large-deformation, elaatic-plastic, rate-dependent polycrystalline model of crystal plasticity. Different plastic anisotropy due to different orientation of each crystal makes inhomogeneous deformation. Assuming plane strain compression condition, the simulation with a high rate sensitivity resulted in main component change from Dillamore at low rate sensitivity to Brass component.

• Journal of the Korean Ceramic Society
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• v.26 no.6
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• pp.795-801
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• 1989

The polycrystalline mullite fiber was synthesized from various combination of starting materials including metal alkoxides and colloidal sol by the sol-gel process. The best spinnability was observed in the sol which showed shear thinning and hysteresis (i.e., thixotropic flow), indicating that the network structure was broken down as the shear rate increased. The mullite fiber was polycrystalline after firing and characterized by thermal analysis, XRD, FT-IR spectroscopy, rheological measurements, and SEM.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09b
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• pp.1309-1310
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• 2006

High-purity and super-hard nano-polycrystalline diamond has been successfully synthesized by direct conversion from high-purity graphite under static pressures above 15 GPa and temperatures above $2300^{\circ}C$. This paper describes research findings on the formation mechanism of nano-structure and on the contributing factor leading to high hardness.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.370-375
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• 1986

In this paper, modeling of the conduction mechanism of ion implanted p-type polycrystalline silicon is studied. From this modeling, the resistivity of p-type polycrystalline and its dependence on dopant concentration are calculated. The proposed modeling whose grain size is about 1450 \ulcorneris shwon to agree well with the experimental result.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.49.1-49.1
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• 2010

본 연구에서는 증착법에 의해 제조된 다결정 실리콘을 이용한 태양전지 제작과 관련하여 다결정 실리콘 씨앗층 제조를 위한 기판에 대하여 연구를 수행하였다. 다결정 실리콘 씨앗층을 제조할 수 있는 기술중 aluminum-induced layer exchange(ALILE) 공정을 이용하여 다결정 실리콘 씨앗층을 제조하였다. glass/Al/oxide/a-Si 구조로 알루미늄과 비정질 실리콘 계면에 알루미늄 산화막을 다양한 두께로 형성시켜, 알루미늄 유도 결정화에서 산화막의 두께가 결정화 특성에 미치는 영향, 결정결함, 결정크기에 대하여 연구하였다. 형성된 다결정 실리콘 씨앗층 막의 특성은 OM, SEM, FIB, EDS, Raman spectroscopy, XRD, EBSD 을 이용하여 분석하였다. 그 결과 산화막의 두께가 증가할수록 결함도 함께 증가하였다. 16nm 두께의 산화막 구조에서 <111> 방향의 우선배향성을 가진, $10{\mu}m$의 sub-grain 결정립을 갖는 씨앗층을 제조 하였다.

• The Korean Journal of Ceramics
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• v.4 no.2
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• pp.122-127
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• 1998

Conductivities of polycrystalline ceria doped with several rare earth oxides were measured by AC admittance and DC four probe method. The conductions were separated into grain and grain boundary contributions using the complex admittance technique as well as grain size dependence of conductivity. The grain size dependence of polycrystalline conductivity, which can be adequately described by the so-called brick layer model, appears to give a more reliable measure of the grain conductivity compared to the complex admittance method. Polycrystalline resistivity(1/conductivity) increases linearly with the reciprocal of grain size. The intercept of resistivity vs. inverse grain size plot gives a measure of the grain resistivity and the slope gives a measure of the grain boundary resistivity. It was also noted that errors involved in the analysis of experimental data may be different between the complex admittance method and the impedance method. A greater resolution of the spectra was found in the complex admittance method, insofar as the present work is concerned, suggesting that the commonly used equivalent circuit may require re-evaluation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.