• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.205-207
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• 2008

The new process for hybrid silicon thin film transistor (TFT) using DPSS laser has been developed for realizing both low-temperature poly-Si (LTPS) TFT and a-Si:H TFT on the same substrate as a backplane of active matrix liquid crystal display. LTPS TFTs are integrated on the peripheral area of the panel for gate driver integrated circuit and a-Si:H TFTs are used as a switching device for pixel in the active area. The technology has been developed based on the current a-Si:H TFT fabrication process without introducing ion-doping and activation process and the field effect mobility of $4{\sim}5\;cm^2/V{\cdot}s$ and $0.5\;cm^2/V{\cdot}s$ for each TFT was obtained. The low power consumption, high reliability, and low photosensitivity are realized compared with amorphous silicon gate driver circuit and are demonstrated on the 14.1 inch WXGA+ ($1440{\times}900$) LCD Panel.

• 한국재료학회지
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• 제28권8호
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• pp.440-444
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• 2018

An effective cleaning method for Ni removal in Ni-induced lateral crystallization(Ni-MILC) poly-Si TFTs and their electrical properties are investigated. The HCN cleaning method is effective for removal of Ni on the crystallized Si surface, while the nitric acid treatment results decrease by almost two orders of magnitude in the Ni concentration due to effective removal of diffused Ni mainly in the poly-Si grain boundary regions. Using the HCN cleaning method after the nitric acid treatment, re-adsorbed Ni on the Si surfaces is effectively removed by the formation of Ni-cyanide complexions. After the cleaning process, important electrical properties are improved, e.g., the leakage current density from $9.43{\times}10^{-12}$ to $3.43{\times}10^{-12}$ A and the subthreshold swing values from 1.37 to 0.67 mV/dec.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.36-39
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• 2002

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays (AMLCD), allowing the integration of both active matrix and driving circuit on the same substrate (normally glass). As high temperature process is not used for glass substrate because of the low softening points below 450$^{\circ}C$. However, high temperature process is required for getting high crystallization volume fraction (i.e. crystallinity). A poly-Si thin film transistor has been fabricated to investigate the effect of high temperature process on the molybdenum (Mo) substrate. Improve of the crystallinity over 75% has been noticed. The properties of structural and electrical at high temperature poly-Si thin film transistor on Mo substrate have been also analyzed using a sputtering method

• 인포메이션 디스플레이
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• 제5권1호
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• pp.13-18
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• 2004

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.293-293
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• 2009

• 인포메이션 디스플레이
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• 제6권5호
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• pp.10-16
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• 2005

• 한국재료학회:학술대회논문집
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• 한국재료학회 1992년도 춘계학술발표회
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• pp.64-64
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• 1992

• 인포메이션 디스플레이
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• 제8권3호
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• pp.18-22
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• 2007

• 한국재료학회지
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• 제18권9호
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• pp.507-510
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• 2008

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.