• 제목/요약/키워드: poly-Si

검색결과 1,077건 처리시간 0.033초

경제적인 Si 잉곳 생산을 위한 poly-Si 미세분말의 성형과 용해주조기술 (Consolidation and casting technology of fine poly-Si powders for economical production of Si ingot)

  • 문병문;김봉환;신제식;이상목;박기성;김대석;김기영
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2007년도 춘계학술대회
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    • pp.261-264
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    • 2007
  • In this study, the consolidation and casting processes of fine Si powders, by-products of making high purity Poly-Si rods in the current method, were systematically investigated for use as economical solar-grade feedstock. Morphology, size, and contamination type of the poly-Si fine powders were inspected by combined analysis of SEM, particle size analyzer, and FT-IR. Poly-Si powder compacts were tried to fabricate by a consolidation process without a binding agent and then their density ratio and strength were evaluated. Finally, the electrical resistivity of the specimens prepared by an electromagnetic casting method was examined for purity assessment.

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실리콘의 이중증착에 의한 산화막 신뢰성 향상 (Reliability Improvement of Thin Oxide by Double Deposition of Silicon)

  • 박진성;양권승
    • 한국세라믹학회지
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    • 제31권1호
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    • pp.74-78
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    • 1994
  • Degradation of thin oxide by doped poly-Si and its improvement were studied. The gate oxide can be degraded by phosphorous in poly-Si doped POCl3. The degradation is increased with the decrement of sheet resistance and poly-Si thickness. Oxide failures of amorphous-Si are higher than those of poly-Si. In-situ double deposition of amorphous-Si, 54$0^{\circ}C$/30 nm, and poly-Si, 6$25^{\circ}C$/220 nm, forms the mismatch structure of grain boundary between amorphous-Si and poly-Si, and suppresses the excess phosphorous on oxide surface by the mismatch structure. The control of phosphorous through grain boundary improves the oxide reliability.

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Improvement in Electrical Stability of poly-Si TFT Employing Vertical a-Si Offsets

  • Park, J.W.;Park, K.C.;Han, M.K.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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    • pp.67-68
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    • 2000
  • Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

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ULG 및 ELA Poly-Si TFTs의 게이트-바이어스 스트레스에 따른 비교 연구

  • 김지웅;김태용;이준신
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.264.1-264.1
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    • 2014
  • 현재 디스플레이에서 가장 널리 이용되는 ELA poly-Si TFT의 표면 거칠기 등으로 인한 대면적 문제를 해결하고자 연구 중인 MIC 방식의 ULG poly-Si TFT를 이용한 게이트-바이어스 스트레스에 따른 전기적 특성을 비교하고자 한다. Positive gate bias의 경우 20V의 게이트 전압과 -0.1V의 드레인 전압에서 10,000초 동안 비교 측정하였으며, 이때 ${\Delta}VTH$는 ELA poly-Si TFT가 143.6 mV, ULG poly-Si TFT가 28.8 mV였다. 또한 negative gate bias의 경우 -20 V의 게이트 전압과 -0.1 V의 드레인 전압에서 10,000초 동안 비교 측정하였으며, 이때 ${\Delta}VTH$는 ELA poly-Si TFT가 154.4 mV, ULG poly-Si TFT가 70.8 mV였다. 이는 게이트 절연막과 채널층 사이의 계면에서 높은 표면 거칠기로 인한 전계의 차이에 의해 더 많은 전하의 트랩에 기인한 것이다.

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고상 결정화에 의해 제작된 다결정 실리콘 박막의 특성 연구 (A Study on the characteristics of polycrystalline silicon thin films prepared by solid phase cyrstallization)

  • 김용상
    • E2M - 전기 전자와 첨단 소재
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    • 제10권8호
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    • pp.794-799
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    • 1997
  • Poly-Si films have been prepared by solid phase crystallization of LPCVD(low-pressure CVD) amorphous silicon. The crystallinity of poly-Si films has been derived from UV reflectance spectrum and lies in the range between 70% and 80% . From XRD measurement the peak at 28.2$^{\circ}$from (111) plane is dominantly detected in the SPC poly-Si films, The average grain size of poly-Si film is determined by the image of SEM and varies from 4000 $\AA$ to 8000$\AA$. The electrical conductivity of as-deposited amorphous silicon film is about 2.5$\times$10$^{-7}$ ($\Omega$.cm)$^{-1}$ , and 3~4$\times$10$^{-6}$ ($\Omega$.cm)$^{-1}$ of room temperature conductivity is the SPC poly-Si films. The conductivity activation energies are 0.5~0.6 eV or the 500$\AA$-thick poly-Si films.

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Effect of Density-of-States (DOS) Parameters on the N-channel SLS Poly-Si TFT Characteristics

  • Ryu, Myung-Kwan;Kim, Eok-Su;Son, Gon;Lee, Jung-Yeal
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.718-722
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    • 2006
  • The dependence of n-channel 2 shot SLS poly-Si TFT characteristics on the DOS (density of states) parameters was investigated by using a device simulation. Device performances were most sensitive to the DOS of poly-Si/gate insulator (GI) interface and poly-Si active layer. Deep level states at the poly-Si/GI interfaces strongly affect the subthreshold slope.

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Characteristics of poly-Si TFTs Required for System-on-Glass Analog Circuits

  • Kim, Dae-June;Lee, Kyun-Lyeol;Yoo, Chang-Sik
    • Journal of Information Display
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    • 제5권4호
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    • pp.1-6
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    • 2004
  • In this paper, we investigate on the characteristics of poly-Si TFTs reuired for the implementation of analog circuits to be integrated with System-on-Glass (SoG). Matching requirements in terms of resistor values, threshold voltage and mobility of poly-Si TFTs are derived as a function of the resolution of display system. Effective mobility of poly-Si TFTs required for the realization of source driver is analyzed for various panel sizes.

다결정 3C-SiC 박막의 기계적 특성 (Mechanical Characteristics of Poly 3C-SiC Thin Films)

  • 한기봉;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.359-360
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    • 2007
  • In this paper, the elastic modulus and hardness of poly 3C-SiC thin films growed by APCVD were measured using nanoindentation test. The resulting values of elastic modulus E and hardness H of the poly 3C-SiC film are 305 GPa and 26 GPa, respectively. The mechanical properties of the poly 3C-SiC film are better than bulk Si wafers. Therefore, the poly 3C-SiC thin film is suitable for abrasion resistance, high frequency, and bio MEMS applications.

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역 알루미늄 유도 결정화 공정을 이용한 실리콘 태양전지 다결정 시드층 생성 (Fabrication of Poly Seed Layer for Silicon Based Photovoltaics by Inversed Aluminum-Induced Crystallization)

  • 최승호;박찬수;김신호;김양도
    • 한국재료학회지
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    • 제22권4호
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    • pp.190-194
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    • 2012
  • The formation of high-quality polycrystalline silicon (poly-Si) on relatively low cost substrate has been an important issue in the development of thin film solar cells. Poly-Si seed layers were fabricated by an inverse aluminum-induced crystallization (I-AIC) process and the properties of the resulting layer were characterized. The I-AIC process has an advantage of being able to continue the epitaxial growth without an Al layer removing process. An amorphous Si precursor layer was deposited on Corning glass substrates by RF magnetron sputtering system with Ar plasma. Then, Al thin film was deposited by thermal evaporation. An $SiO_2$ diffusion barrier layer was formed between Si and Al layers to control the surface orientation of seed layer. The crystallinity of the poly-Si seed layer was analyzed by Raman spectroscopy and x-ray diffraction (XRD). The grain size and orientation of the poly-Si seed layer were determined by electron back scattering diffraction (EBSD) method. The prepared poly-Si seed layer showed high volume fraction of crystalline Si and <100> orientation. The diffusion barrier layer and processing temperature significantly affected the grain size and orientation of the poly Si seed layer. The shorter oxidation time and lower processing temperature led to a better orientation of the poly-Si seed layer. This study presents the formation mechanism of a poly seed layer by inverse aluminum-induced crystallization.