• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.121-122
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• 2006

Recently, poly-Si TFT-LCD starts to be mass produced using excimer laser annealing (ELA) poly-Si. The main reason for this is the good quality poly-Si and large area uniformity. We report the influence of channel length and width on poly-Si TITs performance. Transfer characteristics of n-channel poly-Si thin film transistors fabricated on polycrystalline silicon (poly-Si) thin film transistors (TFTs) with various channel lengths and widths of $2-30{\mu}m$ has been investigated. In this paper, we analyzed the data of n-type TFTs. We studied threshold voltage ($V_{TH}$), on/off current ratio ($I_{ON}/I_{OFF}$), saturation current (I_{DSAT}$), and transconductance ($g_m$) of n-channel poly-Si thin film transistors with various channel lengths and widths.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.55.2-55
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• 1998

다견정 심리판-거l르마늄(JXlly-SiGe)은 TFT(thin-film transistor)와 갇븐 소자 응용에 있어서 중요한 불칠이다 .. LPCVD (low pressure chemical vapor deposition) 방법으로 비정칠 SiGc (a-SiGe) 박막올 증 착시키고 고상결정화(SPC: solid-phase crystallization)시켜 poly-SiGc옹 얻는 것은 잘 알려져 있다. 그러 나 그러나 PF'||'&'||'pound;VD-SPC 방법올 이용한 poly-SiGc의 제조에 대해서는 아직 두드러지게 연구된 바 없다. 우리단 PF'||'&'||'pound;VD 방법으로 a-SiGc 박막올 증착시키고 고상캘정화시켜 poly-SiGc올 얻었 R며, :~ 결정성, G Gc 농도, 결정핍의 평끌 크기 눔올 XRD (x-ray diffraction) 방법으호 조사하였다. 특히 pr'||'&'||'pound;VD 증착시 가판온도,Gc 함유량 등이 고상화에 미치는 영향에 대해서 조사하였다. P PECVD 장치는 터보펌프콸 사용하여 71저진공이 2xlOlongleftarrow5 Torr에 이르렀다. 가판윤 SiOOO) 웨이퍼륜 사용하고 기판 온도는 약 150- 35()"C 사이에서 변화되었다. 증착가스는 SiH4, GcH4, 112 등흘 썼다. 증착 압력과 r.f 전력용 각각 O.25ToIT와 3W로 일정하게 하였다 .. Gc 함유량(x)은 x x=O.O-O.5 사이에서 변화되었다 .. PECVD모 증착된 SiGc 박막들은 고상결정화를 위해 $\theta$X)"(:: Nz 분위기에서 24시간동안, 혹은 5OO'C에서 4열간 가열되었다. 고상결정화 후 poly-SiGc 박막은 SiGc(Ill), (220), (311) XRD 피크들올 보여주었으며, 각 피 크들은 poly-Si에 비하여 왼쪽으로 Bragg 각이 이동되었고, Vegard’slaw에 의해서 x의 값올 확 인할 수 있었다. 이것온 RBS 결과와 열치하였다. 약 150-350'C 사이에서 변화된 기판온도의 범위 에서 증착온도가 낮올수콕 견정립의 크기는 대체로 증가하는 것으로 나타났다 .. XHD로 추정된 형 균 결정립의 크기는 최대 약 3$\alpha$1m 정도였다. 또한 같끈 샘플뜰에 대해서 기판온도가 낮올수록 증착속도가 증가함옴 확인하였다 .. Gc 함유량이 x=O.1에서 x=O.5로 증가함에 따라서도 결정립의 크기와 SiGc 증착속도는 증가하는 것으로 나타났다 .. Hwang [1] , Kim[2] 둥의 연구자들은 Gc 함유 량이 증가함에 따라 결정 립 크기가 캄소하는 것올 보고하였으냐, Tsai [3] 둥은 반대의 결과플 보 고하고 Ge 힘유량의 증가시 결정립 크기의 증가에 대해 Gc의 Si보다 낮은 융점 (melting point) 올 강조한 바 있다. 결정립 크기의 증가는 대체로 SiGe 중착속도의 증가와도 관련이 있음올 볼 때, poly-SiGc의 경우에도 polv-Si의 고상화에서와 같이 증착속도가 빠를수록 최종적언 결정럽의 크기가 커지는 것으로 이해될 수도 있다 .. PECVD 증착시 증착속도의 증가는 증착된 박딱에서의 무켈서도를 증 가시킬 수 있음올 고려하면, 이라한 결파플온 p이y-SiGc의 고상결정화에서도 ploy-Si의 고상결정 화에서와 마찬가지로 초기 박막에서의 구조직 무절서도가 클수록, 고상결정화 후 결정 립의 크기 가 커칠 수 있음올 보여준다고 생각휠 수 있다,

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.331-332
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• 2007

Surface micromachined SiC devices have readily been fabricated from the polycrystalline (poly) 3C-SiC thin film which has an advantage of being deposited onto $SiO_2$ or $Si_3N_4$ as a sacrificial layer. Therefore, in this work, magnetron reactive ion etching process which can stably etch poly 3C-SiC thin films grown on $SiO_2$/Si substrate at a lower energy (70 W) with $CHF_3$ based gas mixtures has been studied. We have investigated the etching properties of the poly 3C-SiC thin film using PR/Al mask, according to $O_2$ flow rate, pressure, RF power, and electrode gap. The etched RMS (root mean square), etch rate, and etch profile of the poly 3C-SiC thin films were analyzed by SEM, AFM, and $\alpha$-step.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.151-157
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• 1996

We propose a mechanism for the formation of pinholes in the Si-buffer layer, through the observations with varying the process- and structure variables in the SEPOX (selective poly-oxidation) process, an isolation method for sub-u DRAMs. Pinholes are formed through the accumulation of Si vacancies generated by the oxidation of Si, in which Si atoms leave the sites (vacancies) at the Si/SiO$_{2}$ interfaces and diffuse into the oxide to be oxidized near interface. In the course of the accumulation of Si-vacancies, the stress induced in the Si-buffer layer affects the migration of vacancies to result in the final size and distribution of pinholes. This paper may be, to our knowledge, the first report about the oxidation-induced pinhole in the Si/SiO$_{2}$ system.

• Korean Journal of Materials Research
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• v.28 no.8
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• pp.440-444
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• 2018

An effective cleaning method for Ni removal in Ni-induced lateral crystallization(Ni-MILC) poly-Si TFTs and their electrical properties are investigated. The HCN cleaning method is effective for removal of Ni on the crystallized Si surface, while the nitric acid treatment results decrease by almost two orders of magnitude in the Ni concentration due to effective removal of diffused Ni mainly in the poly-Si grain boundary regions. Using the HCN cleaning method after the nitric acid treatment, re-adsorbed Ni on the Si surfaces is effectively removed by the formation of Ni-cyanide complexions. After the cleaning process, important electrical properties are improved, e.g., the leakage current density from $9.43{\times}10^{-12}$ to $3.43{\times}10^{-12}$ A and the subthreshold swing values from 1.37 to 0.67 mV/dec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.36-39
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• 2002

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays (AMLCD), allowing the integration of both active matrix and driving circuit on the same substrate (normally glass). As high temperature process is not used for glass substrate because of the low softening points below 450$^{\circ}C$. However, high temperature process is required for getting high crystallization volume fraction (i.e. crystallinity). A poly-Si thin film transistor has been fabricated to investigate the effect of high temperature process on the molybdenum (Mo) substrate. Improve of the crystallinity over 75% has been noticed. The properties of structural and electrical at high temperature poly-Si thin film transistor on Mo substrate have been also analyzed using a sputtering method

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.430-431
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• 2006

This letter reports the fabrication of polycrystalline silicon thin-film transistors (poly-Si TFT) on flexible plastic substrates using amorphous silicon (a-Si) precursor films by sputter deposition. The a-Si films were deposited with mixture gas of argon and helium to minimize the argon incorporation into the film. The precursor films were then laser crystallized using XeCl excimer laser irradiation and a four-mask-processed poly-Si TFTs were fabricated with fully self-aligned top gate structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.234-239
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• 2007

This paper describes the TiW ohmic contact characteristics under the surface treatment of the polycrystalline 3C-SiC thin film grown on $SiO_2/Si(100)$ wafers by APCVD. The poly 3C-SiC surface was polished by using CMP(chemical mechanical polishing) process and then oxidized by wet-oxidation process, and finally removed SiC oxide layers. A TiW thin film as a metalization process was deposited on the surface treated poly 3C-SiC layer and was annealed through a RTA(rapid thermal annealing) process. TiW/poly 3C-SiC was investigated to get mechanical, physical, and electrical characteristics using SEM, XRD, XPS, AFM, optical microscope, I-V characteristic, and four-point probe, respectively. Contact resistivity of the surface treated 3C-SiC was measured as the lowest $1.2{\times}10^{-5}{\Omega}cm^2$ at $900^{\circ}C$ for 45 sec. Therefore, the surface treatments of poly 3C-SiC are necessary to get better contact resistance for extreme environment MEMS applications.

• Journal of the Korean Applied Science and Technology
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• v.32 no.4
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• pp.718-723
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• 2015

For the fabrication of the Si negative electrode in Li-ion batteries (LIBs) containing the cross-linking polymer binder, in this work, the urethane acrylate (UA) oligomer was synthesized via a simple synthetic process. The cross-linked poly(urethane acrylate) (CPUA)/carbone black (CB)/Si composite (CPUA/CB/Si composite) was fabricated through reactions between their reactive vinyl segments in the UA oligomer. Interestingly, the CPUA/CB/Si composite showed better cycle performance than the poly(vinylidene fluoride) (PVdF)/CB/Si composite (PVdF/CB/Si composite) and the polyurethane (PU)/CB/Si composite (PU/CB/Si composite). The CPUA/CB/Si composite had the best lithiation of about $2586mAh\;g^{-1}$. The UA oligomer showed a good compatibility with the electrode materials and current collector after and before a curing process.

• Journal of the Korean Electrochemical Society
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• v.3 no.1
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• pp.19-24
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• 2000

It is increasingly necessary to use poly-Si n's as high resolution and integration of Tn for LCD. Excimer Laser Crystallization (ELC) of a-Si is mainly used as a low temperature process. But the ELC method for the fabrication of poly-Si has the eruption problems associated with hydrogen in the a-Si film. So we need a dehydro-genation process additionally. Hydrogen in a-Si film can degrade the quality of poly-Si film and electrical properties of device due to the hydrogen eruption and voids which occur during the excimer laser annealing. In this study, we propose mesh-type PECVD as the a-Si film deposition method for achieving the low concentration hydrogen. Mesh-type PECVD was found to reduce the hydrogen content substantially. We could obtain a as-deposited a-Si film with hydrogen contents less than $1\%$ at $300^{\circ}C$. We also investigated the behavior by XeCl excimer laser annealing of a-Si fabricated by mesh-type PECVB. As a result, we were able to confirm the broad process window in contrast to the narrow process range typically obtained in ELC. Hydrogen eruption was not observed in poly-Si films after ELC These results suggests that mesh-type PECVD is a viable method to achieve the low hydrogen content a-Si and improve the process windows for ELC.