• Title/Summary/Keyword: poly silicon(PS)

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The field emission characteristics of an oxidized porous polysilicon field emitter using Pt/Ti emitter-electrode (Pt/Ti 전극을 사용한 산하된 다공질 폴리 실리콘 전계방출소자의 특성)

  • Han Sang-Kug;Park Keun-Yong;Choi Sie-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.6 s.336
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    • pp.23-30
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    • 2005
  • In this paper, OPPS(oxidized porous poly-silicon) field emitters were fabricated by using various emitter-electrode metal and these electron emission characteristics were investigated for different thermal annealing effects. The addressed OPPS field emitter with Pt/Ti emitter electrode annealed at $300^{\circ}C$-1hr showed the efficiency of $2.98\%$ at $V_{ps}$=12 V and one annealed at $350^{\circ}C$-1hr showed the highest efficiency of $3.37\%$at $V_{ps}$=16V. They are resulted from the improvement of interfacial contact characteristics of thin emitter metal to an oxidized porous poly-silicon and the decrease of electrical resistance of emitter metal. The brightness of the OPPS field emitter increases linearly in $V_{ps}$ and after oxidation process for $900^{\circ}C$-50min, the brightness of the OPPS field emitter with the as-deposited Pt/Ti emitter electrode was 3600 cd/$m^2$ at the $V_{ps}$=15 V, 6260 cd/$m^2$ at the $V_{ps}$=20 V. Thermal treatment improved the adhesion between the Ti buffer layer and the oxidized porous poly-silicon and also played an important role in the uniform distribution of electric field to the emitter electrode.

Fabrication of Nanostructured Films of Block Copolymers for Nanolithographical Masks (나노리소그래피 마스크용 블록공중합체 나노구조 필름의 제조)

  • Park Dae-Ho;Sohn Byeong-Hyeok;Jung Jin Chul;Zin Wang-Cheol
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.2 s.35
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    • pp.181-186
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    • 2005
  • We fabricated thin films of polystyrene-block-poly(methyl methacrylate)(PS -b-PMMA) on the self-assembled monolayers(SAM) of 3-(p-methoxyphenyl)propyltrichlorosilane(MPTS) on silicon wafers. Cylindrical nanodomains of PMMA or PS were oriented perpendicular to the surface of silicon wafers due to the neutral affinity of the SAM to PS and PMMA blocks. By selective removal of the PMMA block with UV irradiation and washing, nanoporous films and nanorod assemblies were produced. The nanoporous film can be used for a nanolithographical mask.

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Porous silicon-based chemical and biosensors (다공질 실리콘 구조를 이용한 화학 및 바이오 센서)

  • Kim, Yun-Ho;Park, Eun-Jin;Choi, Woo-Seok;Hong, Suk-In;Min, Nam-Ki
    • Proceedings of the KIEE Conference
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    • 2005.07c
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    • pp.2410-2412
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    • 2005
  • In this study, two types of PS substrate were fabricated for sensing of chemical and biological substances. For sensing of the humidity and chemical analyzes such as $CH_3OH$ or $C_2H_5OH$, PS layers are prepared by photoelectrochemical etching of silicon wafer in aqueous hydrofluoric acid solution. To evaluate their sensitivity, we measured the resistance variation of the PS diaphragm. As the amplitude of applied voltage increases from 2 to 6Vpp at constant frequency of 5kHz, the resistance variation for humidity sensor rises from 376.3 to $784.8{\Omega}$/%RH. And the sensitivities for $CH_3OH$ and $C_2H_5OH$ were 0.068 uA/% and 0.212 uA/%, respectively. For biological sensing application, amperometric urea sensors were fabricated based on porous silicon(PS), and planar silicon(PLS) electrode substrates by the electrochemical methods. Pt thin film was sputtered on these substrates which were previously formed by electrochemical anodization. Poly (3-methylthiophene) (P3MT) were used for electron transfer matrix between urease(Urs) and the electrode phase, and Urs also was by electrochemically immobilized. Effective working area of these electrodes was determined for the first time by using $Fe(CN)_6^{3-}/Fe(CN)_6^{4-}$ redox couple in which nearly reversible cyclic voltammograms were obtained. The $i_p$ vs $v^{1/2}$ plots show that effective working electrode area of the PS-based Pt thin film electrode was 1.6 times larger than the PLS-based one and we can readily expect the enlarged surface area of PS electrode would result in increased sensitivity by ca. 1.6 times. Actually, amperometric sensitivity of the Urs/P3MT/Pt/PS electrode was ca 0.91uA/$mM{\cdot}cm^2$, and that of the Urs/P3MT/Pt/PLS electrode was ca. 0.91uA/$mM{\cdot}cm^2$ in a linear range of 1mmol/L to 100mmol/L urea concentrations

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Silicon-Organic Hybrid Solar Cell Using Ag Nanowire/PEDOT:PSS Layer (은 나노와이어/PEDOT:PSS를 이용한 실리콘-유기물 하이브리드 태양전지)

  • Kyudong Kim;Sungjin Jo
    • Korean Journal of Materials Research
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    • v.34 no.8
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    • pp.395-399
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    • 2024
  • Among various organic materials suitable for silicon-based inorganic-organic hybrid solar cells, poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) has been extensively studied due to its high optical transmittance, high work function, and low bandgap characteristics. The electro-optical properties of PEDOT:PSS have a significant impact on the power conversion efficiency of silicon-organic hybrid solar cells. To enhance the photovoltaic properties of the silicon-organic hybrid solar cells, we developed a method to improve the properties of the PEDOT:PSS film using Ag nanowires (NW) instead of conventional solvent addition methods. The influence of the Ag NW on the electro-optical property of the PEDOT:PSS film and the photovoltaic performance of the silicon-organic hybrid solar cells were investigated. The addition of Ag NW further improved the sheet resistance of the PEDOT:PSS film, enhancing the performance of the silicon-organic hybrid solar cells. The present work using the low sheet resistance PEDOT:PSS layer paves the way to develop simple yet more efficient silicon-organic hybrid solar cells.

Orientational Control of Nano Structures from Block Copolymer Using Homo-Polymer Nano Interface (단일 성분 고분자 나노 계면의 도입을 통한 블락 고분자 박막의 나노 구조 배향 조절)

  • In, Insik
    • Journal of Adhesion and Interface
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    • v.9 no.4
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    • pp.30-33
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    • 2008
  • Two polymeric interfaces with single component homo-polymers were prepared to control the orientation of block copolymer thin-film nanostructures. Poly(4-acetoxy styrene) (OH-PAS) and poly(4-methoxy styrene) (OH-PMS) which have the average chemical composition of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) were precisely synthesized through nitroxide-mediated radical polymerization. After dehydration reactions between above polymers and SiOx layers of silicon wafers, the polymer-modified interface induced partial (30%) vertical orientation of PS-b-PMMA thin film in the case of OH-PMS and wholly parallel orientation in the case of OH-PAS. Chemical compositions of polymeric interface layers are regarded as the key parameter to control the orientation of nanostructures of block copolymer thin film.

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Orientation of Poly(styrene-b-methylmethacrylate) thin films deposited on Self-Assembled Monolayers of phenylsilanes

  • Kim, Rae-Hyun;Bulliard, Xavier;Char, Kook-Heon
    • Proceedings of the Polymer Society of Korea Conference
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    • 2006.10a
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    • pp.311-311
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    • 2006
  • The morphology of Poly(styrene-b-methylmethacrylate) (P(S-b-MMA)) block copolymer thin films deposited on silicon wafers was controlled by treating the substrates with Self-Assembled Monolayers (SAM) of phenylsilanes with different alkyl chain lengths. It was found that the treatment with SAM strongly modified the substrates properties, especillay the surface energy, as compared with bare silicon oxide. By futher adjusting the molecular weight of P(S-b-MMA), a variety of morphologies could be generated, including a perpendicular orientation of lamellea of PS and PMMA, which is required for industrial applications.

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Effect of the Hydrophobicity of Hybrid Gate Dielectrics on a ZnO Thin Film Transistor

  • Choi, Woon-Seop;Kim, Se-Hyun
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.6
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    • pp.257-260
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    • 2010
  • Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

A simple model and parameter extraction method for the description of ON-current of LT-PS TFT

  • Chung, De-Will;Park, Jun-Young;Park, Sang-Gyu
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.759-762
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    • 2006
  • A simple SPICE model for the description of the on-current of low-temperature poly-silicon thin film transistors is proposed. By employing constant mobility, $V_GS$ dependent alpha parameter, and exponential kink effect, very good agreements between the model and measurement were obtained.

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Surface Micelle Formation of Polystyrene-b-Poly(2-vinyl pyridine) Diblock Copolymer at Air-Water Interface

  • Park, Myunghoon;Bonghoon Chung;Byungok Chun;Taihyun Chang
    • Macromolecular Research
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    • v.12 no.1
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    • pp.127-133
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    • 2004
  • We have studied the surface micelle formation of polystyrene-b-poly(2-vinyl pyridine) (PS-b-P2VP) at the air-water interface. A series of four PS-b-P2VPs were synthesized by anionic polymerization, keeping the PS block length constant (28 kg/㏖) and varying the P2VP block length (1, 11, 28, or 59 kg/㏖). The surface pressure-area ($\pi$-A) isotherms were measured and the surface morphology was studied by atomic force microscopy (AFM) after Langmuir-Blodgett film deposition onto silicon wafers. At low surface pressure, the hydrophobic PS blocks aggregate to form pancake-like micelle cores and the hydrophilic P2VP block chains spread on the water surface to form a corona-like monolayer. The surface area occupied by a block copolymer is proportional to the molecular weight of the P2VP block and identical to the surface area occupied by a homo-P2VP. It indicates that the entire surface is covered by the P2VP monolayer and the PS micelle cores lie on the P2VP monolayer. As the surface pressure is increased, the $\pi$-A isotherm shows a transition region where the surface pressure does not change much with the film compression. In this transition region, which displays high compressibility, the P2VP blocks restructure from the monolayer and spread at the air-water interface. After the transition, the Langmuir film becomes much less compressible. In this high-surface-pressure regime, the PS cores cover practically the entire surface area, as observed by AFM and the limiting area of the film. All the diblock copolymers formed circular micelles, except for the block copolymer having a very short P2VP block (1 kg/㏖), which formed large, non-uniform PS aggregates. By mixing with the block copolymer having a longer P2VP block (11 kg/㏖), we observed rod-shaped micelles, which indicates that the morphology of the surfaces micelles can be controlled by adjusting the average composition of block copolymers.

Implementation of a Single Chip CMOS Transceiver for the Fiber Optic Modules (광통신 모듈용 단일 칩 CMOS트랜시버의 구현)

  • 채상훈;김태련
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.11-17
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    • 2004
  • This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.