• 마이크로전자및패키징학회지
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• 제17권3호
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• pp.79-84
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• 2010

3차원 Si 칩 패키징 공정을 위한 비아 홀(TSV: Through-Si-Via) 및 Au 시드층 형성, 전기 도금을 이용한 Cu 충전기술과 범핑 공정 단순화에 관하여 연구하였다. 비아 홀 형성을 위하여 $SF_6$ 와 $C_4F_8$ 플라즈마를 교대로 사용하는 DRIE(Deep Reactive Ion Etching) 법을 사용하여 Si 웨이퍼를 에칭하였다. 1.92 ks동안 에칭하여 직경 40 ${\mu}m$, 깊이 80 ${\mu}m$의 비아 홀을 형성하였다. 비아 홀의 옆면에는 열습식 산화법으로 $SiO_2$ 절연층을, 스퍼터링 방법으로 Ti 접합층과 Au 시드층을 형성하였다. 펄스 DC 전기도금법에 의해 비아 홀에 Cu를 충전하였으며, 1000 mA/$dm^2$ 의 정펄스 전류에서 5 s 동안, 190 mA/$dm^2$의 역펄스 조건에서 25 s 동안 인가하는 조건으로 총 57.6 ks 동안 전기도금하였다. Si 다이 상의 Cu plugs 위에 리소그라피 공정 없이 전기도금을 실시하여 Sn 범프를 형성할 수 있었으며, 심각한 결함이 없는 범프를 성공적으로 제조할 수 있었다.

• 한국생산제조학회지
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• 제22권3호
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• pp.472-479
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• 2013

We carried out research into an environmentally friendly injection molding process that involves filling the mold with polymer after thin films are fixed into the cavity, without the coating, plating process. Film insert injection molding is a new technique in which molten plastic resin is injected into the cavity after films are precisely attached to the side of the mold wall. In the film insert injection molding process, the insert film is moved by the flow of the molten plastic resin. Overlap defects cause a decline in the productivity and the quality of the manufactured goods. To reduce overlap defects, new injection mold parts are proposed to produce automotive exterior parts using thin films. It is suggested that the best possible method would be to fix the thin films to one side of the mold wall, and develop interior pins to fix the films in the mold. Based on this new pin fixing system, the problem of the film being moved by the flow of the molten resin was improved.

• 연구논문집
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• 통권26호
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• pp.121-132
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• 1996

The carburising surface modification treatment of the die steel has been used for improving wear resistance and heat cycle strength of the die and preventing a pitting on the surface because the carbides are forming in the matrix during carburising. Generally, the hot forging die was used after quenching-tempering treatment or nitriding after quenching-tempering treatment. The nitriding after carburising on the surface of a hot die steel and a wear resistance die steels was suggested by SOUCHARD, JACQUOT. and BUVRON. This surface modification treatment improved the adhesive and abrasive wear resistance and friction coefficient. The process was introduced to the forging die of stainless steel, titanium alloy steel, alloy and medium carbon steel and the physical properties of the die after the treatment were improved. The surface hardening treatment of the nitriding, the carburising, the boriding, and TD process were used to improved the life time of the forging die. Also, the coating process of PVD, CVD and PCVD were used and the hard chromium plating was occasionally used. Therefore, this study analyzed the effects of the carburising time and the conditions of nitriding on STD61 steel. The case depth, the surface hardness, the forming carbide size and shape during overcarburising process on the die steel were also examined.

• International Journal of Precision Engineering and Manufacturing
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• 제4권4호
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• pp.51-56
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• 2003

Generally, the build-up printed circuit board manufactured by a sequential process involving etching, plating, drilling, etc, which requires many types of equipments and long lead time. Etching process is suitable for mass production, however, it is not adequate for manufacturing a prototype in the development stage. In this study, we introduce a screen printing technology for prototyping a build-up printed circuit board. As for the material, photo/thermal curable resin and conductive paste are used for the formation of dielectric and conductor. The build-up structure is made by subsequent processes such as formation of a liquid resin thin layer, solidification by a UV/IR light, and via hole filling with a conductive paste. By use of photo curable resin, productivity is greatly enhanced compared with thermal curable resin. Finally, the basic concept and the possibility of build-up printed circuit board prototyping are proposed in comparison with the conventional process.

• Korean Chemical Engineering Research
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• 제43권1호
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• pp.53-59
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• 2005

본 연구에서는 계면활성제를 이용하여 초임계이산화탄소와 전해도금액의 매크로에멀젼을 형성한 후 양극과 음극을 통해 통전시켜 초임계에멀젼 전해도금을 수행하였다. 계면활성제로는 친이산화탄소기와 친수기를 동시에 지닌 sodium salt of bis (2,2,3,3,4,4,5,5-octafluoro-1-pentanol) sulfosuccinate를 사용하였으며 (+)극과 (-)극으로 니켈판과 구리판을 각각 사용하였다. 초임계매크로에멀젼 상태에서 도금된 니켈표면과 기존의 상압 상태에서 도금된 니켈표면을 비교해 본 결과 이산화탄소/니켈도금액 매크로에멀젼에 의해 도금된 니켈표면은 기존 방법에 의한 것보다 더 균일하였다. 계면활성제의 농도와 도금액 양이 도금에 미치는 영향을 살펴보기 위하여 도금액에 첨가한 계면활성제의 농도를 2, 4, 7 wt% 변화시켰으며 도금 반응셀 내에서 차지하는 도금액의 부피를 10 vol%에서 70 vol%까지 증가시켰다. 그리고 연속상의 영향을 알아보기 위하여 초임계이산화탄소 대신에 프로판을 사용하여 그 결과를 살펴보았다. 매크로에멀젼이 형성되는 농도 이상에서는 계면활성제의 농도가 높아질수록 전류량과 도금되는 니켈 양이 모두 감소하였으며, 도금액의 부피가 증가할수록 전류량과 전기전도도가 높아지고 도금되는 니켈 양이 증가하였다. 또한, 연속상의 경우, 프로판보다 이산화탄소가 우수한 도금효과를 보임을 알 수 있었다.

• ETRI Journal
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• 제25권2호
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• pp.65-72
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• 2003

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.

• 한국레이저가공학회지
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• 제16권4호
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• pp.12-16
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• 2013

For mass production of electronic devices, the processing of the printing roll is one of the most important key technologies for printed electronics technology. A roll of printing process, the gravure printing that is used to print the electronic device is most often used. The indirect laser processing has been used in order to produce printing roll for gravure printing. It consists of the following processing that is coating of photo polymer or black lacquer on the surface of printing roll, pattering using a laser beam and etching process. In this study, we have carried out study on the coating and etching for $25{\mu}m$ line width on the printing roll. To do this goals, a $4{\mu}m$ coating thickness and 20% average coating thickness of the coating homogeneity of variance is performed. The factors to determine the thickness and homogeneity are a viscosity of coating solution, the liquid injection, the number of injection, feed rate, rotational speed, and the like. After the laser patterning, a line width of $25{\mu}m$ or less was confirmed to be processed through etching and the chromium plating process.

• 한국전기전자재료학회논문지
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• 제23권12호
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• pp.919-923
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• 2010

Copper pillar tin bump (CPTB) was developed for high density chip interconnect technology. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM -1250 dry film photoresist (DFR), copper electroplating method and Sn electro-less plating method. Mechanical shear strength measurements were introduced to characterize the bonding process as a function of thermo-compression. Shear strength has maximum value with $330^{\circ}C$ and 500 N thenno-compression process. Through the simulation work, it was proved that when the copper pillar tin bump decreased in its size, it was largely affected by the copper oxidation.

• Transactions on Electrical and Electronic Materials
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• 제15권2호
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• 열처리공학회지
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• 제25권6호
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• pp.283-291
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• 2012

In order to increase the anti-oxidation property during the tailor welding blanked hot press forming process for a high strength boron steel sheet, we performed a different coating method on the boron-steel sheet such as 87% Al - 13% Si and Fe - 8.87 Zn dipping plating procedure. However, during laser welding process, the Al-Si coated steel sheet has showed a low tensile strength and about half value of elongation than the original boron-steel sheet. Aluminum and silicon, elements of coating layer were diffused into the boron-steel matrix and have shown a low strength result than non-coated specimen. On the other hand, Zinc-coated boron-steel has expectedly showed a excellent tensile strength and micro-harness value in the welded area like original boron-steel.