• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.367-369
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• 2002

We have designed ramp profile excitation pulse based on the Shinnar-Le Roux (SLR) algorithm. The algorithm provides many advantages to pulse designers. The first advantage is the freedom of deciding the amplitudes, frequencies, and ripple sizes of stopband, passband, and transition band of pulse profile. The second advantage is the freedom of deciding the pulse phase, more specifically, minimum phase, linear phase, maximum phase, and any phase between them. The minimum phase pulse is the best choice in the case of 3D TOF, because it minimizes the echo time, which implies the best image quality in the same MR examination condition. In addition, the half echo technique is slightly modified in our case. In general, using the half echo technique means that the acquired data size is half and the rest part can be filled with complex conjugate of acquired data. But in our case, the echo center is just shifted to left, which implies the reduction of echo time, and the acquired data size is the same as the one without using the half echo technique. In this case, the increase of right part of data leads to improvement of the resolution and the decrease of left part of data leads to decrease of signal to noise ratio. Since in the case of 3D TOF, the signal to noise ratio is sufficiently high and the resolution is more important than signal to noise ratio, the proposed method appears to be significantly affective and gives rise to the improved high resolution angiograms.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.11
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• pp.611-621
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• 2002

For real-time systems, multiprocessor support is indispensable to handle the large number of requests. Existing real-time on-line scheduling algorithms such as Earliest Deadline First Algorithm (EDF) and Least Laxity Algorithm (LLA) may not be suitable for scheduling real-time tasks in multiprocessor systems. Although EDF has low context switching overhead, it suffers from "multiple processor anomalies." LLA has been shown as suboptimal, but has the potential for higher context switching overhead. Earliest Deadline Zero Laxity (EDZL) solved somewhat the problems of those algorithms, however is suboptimal for only two processors. Another algorithm EDA2 shows very good performance in overload phase, however, is not suboptimal for muitiprocessors. We propose two on-line scheduling algorithms, Earliest Deadline/Least Laxity (ED/LL) and ED2/LL. ED/LL is suboptimal for multiprocessors, and has low context switching overhead and low deadline miss rate in normal load phase. However, ED/LL is ineffective when the system is overloaded. To solve this problem, ED2/LL uses ED/LL or EDZL in normal load phase and uses EDA2 in overload phase. Experimental results show that ED2/LL achieves good performance in overload phase as wet] as in normal load phase.oad phase.

• Journal of Ocean Engineering and Technology
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• v.23 no.4
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• pp.52-57
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• 2009

The effect of aging treatment on the microstructure and mechanical properties of super duplex stainless steel with W was investigated. The phase was precipitated mainly at the early stage of aging and a lower aging temperature under $750^{\circ}C$, but the phase was formed after long-term aging treatment between $600^{\circ}C$ and $900^{\circ}C$. The volume fraction of the phase increased with aging temperature up to $750^{\circ}C$ and then decreased up to $900^{\circ}C$. With an increase in the aging time, the volume fraction phase at the early stage of aging increased slightly, and then increased rapidly beyond a certain time. The rapid increase in the tensile strength and hardness and decrease in the elongation and impact toughness were measured with aging temperatures up to $750^{\circ}C$. On the other hand, the tensile strength and hardness decreased slightly, and the elongation and Charpy impact toughness were unchanged with aging temperatures over $750^{\circ}C$. The tensile strength and hardness increased rapidly at the early stage of aging, and then increased slowly beyond a certain time. The elongation and Charpy impact toughness decreased rapidly at the early stage of aging, and then remained unchanged beyond a certain time. The phase that formed at the early stage of aging and the lower aging temperature had a considerable effect on the elongation and Charpy impact toughness of the super duplex stainless steel with W.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Polymer(Korea)
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• v.35 no.2
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• pp.130-135
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• 2011

Along with the fast development of electronics, the demands of portable electronics and wireless sensors are growing rapidly. The need for self-powering materials capable of powering the electrical devices attached to them is increasing, The piezoelectric effect of polyvinylidene fluoride (PVDF) can be used for this purpose. PVDF has a special crystal structure consisting of a ${\beta}$-phase that can produce piezoelectricity. In this paper, multilayer PVDF films were fabricated to increase the ${\beta}$-phase content. A solution of 10% concentration N;N-dimethylacetamide (DMAc) in PVDF (PVDF/DMAc) was used to fabricate the films via spin coating technique with the following optimum process parameters: a spin rate of 850 rpm, spin time of 60 s, drying temperature of $60^{\circ}C$, and drying time of 30 min, Compared with single-layer PVDF films, the multilayer films exhibited higher ${\beta}$-phase content. The ${\beta}$-phase content of the films increased gradually with increasing number of layers until 4, Maximum ratio of ${\beta}$-phase content was 7.72.

• Journal of IKEEE
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• v.11 no.4
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• pp.322-330
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• 2007

Recent advances in wireless networks and low-cost, low-power design have led to active research in large-scale networks of small, wireless, low power sensors and actuators, In large-scale networks, lots of timing-synchronization protocols already exist (such as NTP, GPS), In ad-hoc networks, especially wireless sensor networks, it is hard to synchronize all nodes in networks because it has no infrastructure. In addition, sensor nodes have low-power CPU (it cannot perform the complex computation), low batteries, and even they have to have active and inactive section by periods. Therefore, new approach to time synchronization is needed for wireless sensor networks, In this paper, I propose Energy-Efficient Time Synchronization (EETS) protocol providing network-wide time synchronization in wireless sensor networks, The algorithm is organized two phase, In first phase, I make a hierarchical tree with sensor nodes by broadcasting "Level Discovery" packet. In second phase, I synchronize them by exchanging time stamp packets, And I also consider send time, access time and propagation time. I have shown the performance of EETS comparing Timing-sync Protocol for Sensor Networks (TPSN) and Reference Broadcast Synchronization (RBS) about energy efficiency and time synchronization accuracy using NESLsim.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.9
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• pp.66-72
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• 2005

As one of the methods that determine position using GPS carrier phase without the resolution of integer ambiguity, the characteristics of the time difference is analyzed in this paper. When determining position by the needed accuracy, the difference time gap becomes an important factor. It is said that accuracy is improved as the difference time gap is getting large, and finally the centimeter level accuracy is achieved after a certain difference time gap. In this paper, the characteristics of the time difference is analyzed using real data and a new parameter is proposed to predict the resulting position accuracy. The difference time gap when position error is converged to the centimeter level is estimated with the proposed parameter.

• Journal of Power Electronics
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• v.8 no.3
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• pp.201-209
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• 2008

This paper presents the modeling and design of a digital controller for a phase-shifted full-bridge converter (PSFBC) in a discrete-time domain. The discretized PSFBC model is first derived and then analyzed considering the sampling effect and the system parameters. Based on this model, the digital controller is directly designed in a discrete-time domain. The simulation and experimental results are provided to show the validity of the proposed modeling and controller design.

• The Journal of Information Technology
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• v.12 no.4
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• pp.11-17
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• 2009

In this paper, frequency synthesizer for radar system is designed and developed. Optimizing the phase noise and lock time, each module is designed as two-type PLL circuit, and then the performance of PLL frequency synthesizer is compared. The experiment result shows the lock time of 70 usec, the phase noise of less then 100 dBc, the bandwidth above 500MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.