• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.15-23
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• 2007

A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.11
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• pp.1075-1081
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• 2004

In this paper, a VCO of a general advance warning system for vehicle's speed limitation in the X-band used in Japan is designed using a small signal scattering coefficient of PHEMT. A varactor diode that wide tuning range and series resistance 0 H is used for designing the VCO and -85 dBc/Hz of phase noise at 10 kHz of offset frequency is obtained by adjusting the reflection coefficient between the micro-strip line and the varactor device which determines transistor's operation voltage and resonant frequency, In addition +4.5 dBm of basic frequency signal output level and -25.6 dEc of the second harmonic constraint are acquired. Sample that produce in this paper could confirm that more excellent special quality appears than existing products in sensitivity.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.19-25
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• 2001

In this paper, the design and simulation results of IF frequency synthesizer section has been described. We has been used 0.8 $\mu\textrm{m}$ BiCMOS device and library of the AMS. IF frequency synthesizer section has been contained IF VCO, Phase Detector, Divide_by_8, Charge Pump and Loop Filter. IF frequency synthesizer has been shown operating voltage of 2.7~3.6 V, control voltage of 0.5~2.7 V and supply current of 11 mA. The measured results have been showed good agreement with the simulation results about supply current.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.554-557
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• 1993

The error analysis for the Time-in-Flight Laser Range Finder with Multiple Tone Amplitude Modulation relevant to the phase detection error is made. The distance can be estimated to solve the formulate which express the relationship between the absolute distance from the range finder to the object and the wavenumbers and the phases of the modulated waves by the optimization technique. The main cause of the estimation error can be considered as the phase detection error induced from the amplitude modulator and the phase detector. To clarify the phase detection error and the optimal amplitude frequency set, the numerical analysis are made.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.2
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• pp.168-180
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• 1992

Commumication technology has been continuously developed to overcome the distance and time for the transmission of information to the human society. Wireless mobile communication, which had been used mostly in the military and police is widely used these days for enterprise and individuals. Therefore the domestic usage of the advanced mobile phone service are progressively gaining wide popularity. The modulation techniques used usually in mobile communications were the analog techniques such as AM and FM, but they are getting replaced by the digital techniques, However, the major disadvantage of the digital communications is the increase of the transmission bandwidth. Therefore, it is very important to use efficiently the limited frequency bandwidth. The domestic research and development on the subject seems quite limited and in order to establish the technology of the digital mobile communications. This thesis presents the design of the frequency hopping synthesizer providing 124 channels with a channel spcing of 200KHz. VCD used in the synthesizer employs a semi-rigid cable for higher purity of signal spectrum, and a hybrid pgase detector is realized with a sample hold phase detector in conjuction with a tri-state phase detedctor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.35-43
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• 2011

In this paper, an analysis on I/Q mismatch characteristics of a quadrature LC VCO(Voltage controlled oscillator) is presented. Based on this analysis, a new I/Q mismatch compensator is proposed. The proposed I/Q mismatch compensator utilizes an amplitude mismatch detector rather than the conventional phase mismatch detector requiring much more wide frequency bandwidth. To verify the proposed circuit, a 2.5GHz quadrature LC VCO was designed in a $0.18{\mu}m$ CMOS process and tested. Test results show that an amplitude mismatch detector achieves similar I/Q mismatch compensation performance as that of the conventional phase mismatch detector. The I/Q mismatch compensator consumes 0.4mA from 1.8V supply voltage and occupies $0.04mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.3
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• pp.239-254
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• 1988

In this paper an exciter which performs modulation and amplification is composed of high power(30dBm) VCO(Voltage Controlled Oscillator) using push-pull circuit. Modulation is FSK using PLL(Phase Locked Loop). A single loop PLL synthesizer having sequency range of 42.5-100.5MHz, 25KHz channel spacing and switching time of 1msec converts down the exciter VCO frequency to 1.25MHz. This signal mixed with the FSK modulated signal coming in the phase detector of exciter. The acquisition time of exciter for frequency hoppng is less than 200usec, so the total acquisition time for transmission is less that 1.5msec. There is no need of additional power amplification because power amlifiction by high power VCO is high enough to communicate within near distance. The proposed frequency synthesizer is not complex so it is suitable for low cost slow frequency hopping spread spectrum communication.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.1-6
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• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.