• Wind and Structures
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• v.34 no.5
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• pp.395-405
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• 2022

Tornado-induced damages to high-rise buildings and low-rise buildings are quite different in nature. Tornado losses to high-rise buildings are generally associated with building envelope failures while tornado-induced damages to low-rise buildings are usually associated with structural or large component failures such as complete collapses, or roofs being torn off. While studies of tornado-induced structural damages tend to focus mainly on low-rise residential buildings, transmission towers, or nuclear power plants, the current rapid expansion of city centers and development of large-scale building complexes increases the risk of tornadoes impacting tall buildings. It is, therefore, important to determine how tornado-induced load affects tall buildings compared with those based on synoptic boundary layer winds. The present study applies an experimentally simulated tornado wind field to the Commonwealth Advisory Aeronautical Research Council (CAARC) building and estimates and compares its pressure coefficient effects against the Atmospheric Boundary Layer (ABL) flow field. Simulations are performed at the Wind Engineering, Energy and Environment (WindEEE) Dome which is capable of generating both ABL and tornadic winds. A model of the CAARC building at a scale of 1:200 for both ABL and tornado flows was built and equipped with pressure taps. Mean and peak surface pressures for TLV flow are reported and compared with the ABL induced wind for different time-averaging. By following a compatible definition of the pressure coefficients for TLV and ABL fields, the resulting TLV pressure field presents a similar trend to the ABL case. Also, the results show that, for the high-rise building model, the mean and 3-sec peak pressures are larger for the ABL case compared to the TLV case. These results provide a way forward for the code implementation of tornado-induced pressures on high-rise buildings.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.28-34
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• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.510-518
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• 2010

In this paper, the designed and implemented results of CFL linearization chip which can be used in mobile radio and TRS terminal of UHF band(380~910 MHz), using $0.6\;{\mu}m$ BiCMOS process based on Si, are shown. As gain control circuits for modifying transmit power are inserted not only in feedback path but also in forward path, the stability of CFL is maintained. And, DC-offset correction function of S/H structure, which is suitable for walkie-talkie PTT operation and is easily implemented, is realized. The performance test results of transmitter show that the regulation of FCC emission mask at PEP 3 W(34.8 dBm) is satisfied when the CQPSK modulated signal is fed and more than 30 dBc improvement of 3rd order IMD is achieved when two-tone signal is inputted.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10A
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• pp.807-815
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• 2003

MultiCode-CDMA (MC-CDMA) system of chip level MPSK incorporating with clipper (MP-CDMA)[l] shows constant envelope signal which can mitigate the performance degradation due to nonlinear transmit amplifier. In this paper, modulation is modified to carry out differential encoded MPSK rather than MPSK. The modified system is called DMP-CDMA. DMP-CDMA using differential detection has advantages on receiver complexity and pilot overhead. However, it is inferior to coherent detection by about 4.0dB due to inherent power inefficiency of noncoherent detection and the error propagation. Multiple symbol differential detection is employed in order to improve DMP-CDMA using differential detection. As the result, the performance of DMP-CDMA system is improved about 3.6dB compared to differential detection.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.671-680
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• 2005

The CFL linearisation chip which is one of key devices in ultra-narrowband mobile radio transmitter using CQPSK digital modulation method is designed and implemented with $0.35{\mu}m$ CMOS technology. The reduced size and low cost of transmitter are available by the use of direct-conversion and CFL ASIC chip, which improve the power effi챠ency and linearity of transmitting path. In addition, low power operation is possible through CMOS technology The performance test results of transmitter show -25 dBc improvement of IMD level at the 3 kHz frequency offset and then satisfy FCC 47 CFR 90.210 E emission mask in the operation of CFL ASIC chip. At that time, the transmitting power is about PEP(Peak-to-Envelope Power) 5 W. The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.880-886
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• 2007

We have proposed a new "hybrid" envelope elimination and restoration(EER) transmitter architecture using an efficiency optimized power amplifier(PA) and modified bias modulator. The efficiency of the PA at the average drain voltage is very important for the overall transmitter efficiency because the PA operates mostly at the average power region of the modulation signal. Accordingly, the efficiency of the PA has been optimized at the region. Besides, the bias modulator has been accompanied with the emitter follower for the minimization of memory effect. A saturation amplifier, class $F^{-1}$ is built using a 5-W PEP LDMOSFET for forward-link single-carrier wideband code-division multiple-access(WCDMA) at 1-GHz. For the interlock experiment, the bias modulator has been built with the efficiency of 64.16% and peak output voltage of 31.8 V. The transmitter with the proposed PA and bias modulator has been achieved an efficiency of 44.19%, an improvement of 8.11%. Besides, the output power is enhanced to 32.33 dBm due to the class F operation and the PAE is 38.28% with ACLRs of -35.9 dBc at 5-MHz offset. These results show that the proposed architecture is a very good candidate for the linear and efficient high power transmitter.