• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of Power Electronics
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• v.12 no.5
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• pp.715-722
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• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 1999.10a
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• pp.131-140
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• 1999

Today freeway is experiencing a severe congestion with incoming or outgoing traffic through freeway ramps during the peak periods. Thus, the objectives of this study is to identify the traffic characteristics, analyze the relationships between the traffic characteristics and finally construct the delay predictive models on the ramp junctions of freeway with 70mph speed limit. From the traffic analyses, and model constructions and verifications for delay prediction on the ramp junctions of freeway, the following results were obtained: ⅰ) Traffic flow showed a big difference depending on the time periods. Especially, more traffic flows were concentrated on the freeway junctions in the morning peak period when compared with the afternoon peak period. ⅱ) The occupancy also showed a big difference depending on the time periods, and the downstream occupancy(Od) was especially shown to have a higher explanatory power for the delay predictive model construction on the ramp junction of freeway. ⅲ) The speed-occupancy curve showed a remarkable shift based on the occupancies observed ; Od < 9% and Od$\geq$9%. Especially, volume and occupancy were shown to be highly explanatory for delay prediction on the ramp junctions of freeway under Od$\geq$9%, but lowly for delay predicion on the ramp junctions of freeway under Od<9%. Rather, the driver characteristics or transportation conditions around the freeway were through to be a little higher explanatory for the delay perdiction under Od<9%. ⅳ) Integrated delay predictive models showed a higher explanatory power in the morning peak period, but a lower explanatory power in the non-peak periods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.

• Journal of Korean Port Research
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• v.14 no.2
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• pp.175-185
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• 2000

Today freeway is experiencing a severe congestion with incoming or outgoing traffic through freeway ramps during the peak periods. Thus, the purpose of this study is to identify the traffic characteristics, analyze the relationships between the traffic characteristics and finally construct the delay predictive models on the rap junctions of freeway with 70mph speed limit. From the traffic analyses, and model construction and verification for delay prediction on the ramp junctions of freeway, the following results were obtained : ⅰ) Traffic flow showed a big difference depending on the time periods. Especially, more traffic flows were concentrated on the freeway junctions in the morning peak period. ⅱ) The occupancy also showed a big difference depending on the time periods, and the downstream occupancy(Od) was especially shown to have a higher explanatory power for the delay predictive model construction on the ramp junctions of freeway. ⅲ) The delay-occupancy curve showed a remarkable shift based on the occupancies observed : O$\_$d/〈9% and O$\_$d/$\geq$9%. Especially, volume and occupancy were shown to be highly explanatory for delay prediction on the ramp junctions of freeway under O$\_$d/$\geq$9%, but lowly for delay prediction on the ramp junctions of freeway under O$\_$d/〈9%. Rather, the driver characteristics or transportation conditions around the freeway were thought to be a little higher explanatory for the delay prediction under O$\_$d/〈9%. ⅳ) Integrated delay predictive models showed a higher explanatory power in the morning peak period, but a lower explanatory power in the non-peak periods.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5B
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• pp.365-369
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• 2012

It is very important to control synchronization by inter-network delay compensation in high speed synchronous optcial transmission network systems. In this study we designed a delay measurement system based on OTDR using Rayleigh backscatterer in order to compensate for time delay due to the length of optical fiber line. We observed waveform variations on both averaging time and peak power of laser pulse. Finally, we executed experimental demonstration on its accuracy and test repeatability by comparison to the methods practically used in the industry. Experimental results show maximum error of 0.06usec and standard deviation of 0.021usec, which means it's possibly applied to delay control system for mobile repeaters and stations.

• Corrosion Science and Technology
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• v.21 no.2
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• pp.158-169
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• 2022

The objective of this study was to investigate the electrochemical behavior and damage degree of metal surface under different conditions by performing a potentiodynamic polarization experiment using an electropolishing solution for UNS S31603 based on initial delay time and surface roughness (parameters). A second anodic peak occurred at initial delay time of 0s and 100s. However, it was not discovered at 1000s and 3600s. This research referred to an increase in current density due to hydrogen oxidation reaction among various hypotheses for the second anodic peak. After the experiment, both critical current density and corrosion current density decreased when the initial delay time (immersion time) was longer. As a result of surface analysis, characteristics of the potentiodynamic polarization behavior were similar with roughness, although the degree of damage was clearly different. With an increase in surface roughness value, the degree of surface damage was precisely observed. As such, electrochemical properties were different according to the immersion time in the electropolishing solution. To select electropolishing conditions such as applied current density, voltage, and immersion time, 1000s for initial delay time on the potentiodynamic polarization behavior was the most appropriate in this experiment.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.141-148
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• 2003

This paper presents and compares several techniques that detect the symbol rate of unknown received signal. Symbol rate is detected from the power spectral density of the circuits such as the delay and multiplier circuit, the square law circuit, and analytic signal, etc. As a result of discrete Fourier transform of the output signals of these circuits, a lot of spectral lines and some peaks appear in frequency domain and the position of first peak is corresponding to the symbol rate. If a spectral line on the frequency that is not located in symbol rate is larger than the first peak, the symbol rate is erroneously detected. Thus, the ratio between the value of first peak and the highest side spectral line is used for the measure of the performance of symbol rate detector. For the MPSK modulation, the analytic signal method shows better performance than the delay and multiplier and square law circuits when the received signal power is lager than -20dB. It is also noted that the delay and multiplier circuit is not able to detect the symbol rate for the QAM modulation.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.481-482
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• 2011

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor values at the mode boundary as functions of the input voltage and the time delay.