• ETRI Journal
• /
• v.36 no.5
• /
• pp.876-879
• /
• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.9 no.2
• /
• pp.75-80
• /
• 2014

Energy consumption of sensor nodes is minimized because it has limited energy generator in wireless sensor network. Electronic shelf label system is one of application fields using wireless sensor networks. Battery size of small apparatus for displaying price is restricted. Therefore its current consumption have to be minimized. Furthermore the method for minimization of peak current would be considered because life cycle of coin battery used to display or RF is vulnerable to intensity of drain current. In this paper, we analyze current consumption pattern of low-power electronic shelf label system. Then we propose the method for minimization of current consumption by modification of software and hardware. Current consumption of the system using proposed method are approximately 15 to 20 percent lower than existing system and the life cycle of the system is approximately 10 percent higher than existing system.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.27 no.5
• /
• pp.376-383
• /
• 2022

The improved performance of computer parts, such as graphic card, CPU, and main board, has led to the need for power supplies with a high power output. The dynamic load profile rapidly changes the usage of power consumption depending on load operations, such as PC power and air conditioner. Under dynamic load profile conditions, power consumption can be classified into maximum, normal, and standby power. Several problems arise in the case of maximum power. Peak power is generated at the system power source in the maximum-power situation. Frequent generation of peak power can cause high-frequency problems and reduce the life of high-pressure parts (especially high-pressure capacitors). For example, when a plurality of PCs are used, system overload occurs due to peak power generation and causes problems, such as power failure and increase in electricity bills due to exceeded contract power. To solve this problem, a system peak power limit/compensation power circuit is proposed for a power supply under dynamic load profile conditions. The proposed circuit detects the system current to determine the power situation of the load. When the system current is higher than the set level, the circuit recognizes that the system current generates peak power and compensates for the load power through a converter using a super capacitor as the power source. Thus, the peak power of loads with a dynamic load profile is limited and compensated for, and problems, such as high-frequency issues, are solved. In addition, the life of high-pressure parts is increased.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.1
• /
• pp.43-50
• /
• 2016

NAND flash based storage devices adopts multi-channel and multi-way architecture to improve performance using parallel operation of multiple NAND devices. However, multiple NAND devices consume higher current and peak power overlap problem influences on the system stability and data reliability. In this paper, current waveform is measured for erase, program and read operations, peak current and model is defined by profiling method, and estimated probability of peak current overlap among NAND devices. Also, system level TLM simulator is developed to analyze peak overlap phenomenon depending on various simulation scenario. In order to remove peak overlapping, token-ring based simple power management method is applied in the simulation experiments. The optimal peak overlap ratio is proposed to minimize performance degradation based on relationship between peak current overlapping and system performance.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.1088-1090
• /
• 1993

This paper shows efficient peak demand control method in office buildings. With a rapid growth of national economics and living standard, electrical energy consumption markedly increased. Expecially, it is increased electrical energy comsumption in the office buildings and thus an energy conservation through efficient use of electricity became more important. From the data of electric equipment capacity and electric power consumption for 96 buildings, current levels of demand factor and a growth trend of peak loads by office buildings were surveyed and analyzed. In addition the efficient peak demand control method in office buildings were studied.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1061-1064
• /
• 2009

Through dark injection space-charge-limited current (DI-SCLC) and trap-free SCLC measurements, it has been demonstrated that an indium tin oxide (ITO)/buckminsterfullerene ($C_{60}$) electrode can form a quasi-Ohmic contact with N, N'-bis (naphthalen-1-yl)-N, N'-bis(phenyl) benzidine (NPB). The DI-SCLC results show a clear peak current along with a shift of the peak position as the field intensity varies, implying an Ohmic (or quasi-Ohmic) contact. A theoretical simulation of the SCLC also shows that ITO/$C_{60}$ forms an Ohmic contact with NPB. The Ohmic contact makes it possible to estimate the NPB hole mobility through the use of both DI-SCLC and trap-free SCLC analysis. This also contributes to a reduction in power consumption.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.9 no.3
• /
• pp.137-143
• /
• 2014

Demand Controller is a load control device that monitor the current power consumption and calculate the forecast power to not exceed the power set by consumer. Accurate demand forecasting is important because of controlling the load use the way that sound a warning and then blocking the load when if forecasted demand exceed the power set by consumer. When if consumer with fluctuating power consumption use the existing forecasting method, management of demand control has the disadvantage of not stable. In this paper, load forecasting of the unit of seconds using the Exponential Smoothing Methods, ARIMA model, Kalman Filter is proposed. Also simulation of load forecasting of the unit of the seconds methods and existing forecasting methods is performed and analyzed the accuracy. As a result of simulation, the accuracy of load forecasting methods in seconds is higher.

• ETRI Journal
• /
• v.30 no.4
• /
• pp.612-614
• /
• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• Journal of IKEEE
• /
• v.21 no.4
• /
• pp.331-337
• /
• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.6
• /
• pp.40-44
• /
• 2014

In this paper, maximum power is the lowering device using the facility's energy use and peak load electricity through analyzing attitude should like to make it reduce its power base rate. Simulator to manage the demand for power, a maximum electric power base power from electronic watt-hour meters by a device's signal, predictive power, the current power by computing the goal of power for less than Maximum peak power and peak shift, so that you can manage, and peak York, which role you want a cut Metal heat treatment result which analyzes the data, demand for electricity company over the years of analyzing the characteristics of each load, and effects and Reducing power consumption device every month identified seven Sequence control to the load system and successful power control is about showing that the defined goals.