• 한국전기전자재료학회논문지
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• 제26권11호
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• pp.841-845
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• 2013

We give a textured front on silicon wafer for high-efficiency solar cells by using micro contact printing method which uses PDMS (polydimethylsiloxane) silicon rubber as a stamp and SAM (self assembled monolayer)s as an ink. A random pyramidal texturing have been widely used for a front-surface texturing in low cost manufacturing line although the cell with random pyramids on front surface shows relatively low efficiency than the cell with inverted pyramids patterned by normal optical lithography. In the past two decades, the micro contact printing has been intensively studied in nano technology field for high resolution patterns on silicon wafer. However, this promising printing technique has surprisingly never applied so far to silicon based solar cell industry despite their simplicity of process and attractive aspects in terms of cost competitiveness. We employ a MHA (16-mercaptohexadecanoic acid) as an ink for Au deposited $SiO_2/Si$ substrate. The $SiO_2$ pattern which is same as the pattern printed by SAM ink on Au surface and later acts as a hard resist for anisotropic silicon etching was made by HF solution, and then inverted pyramidal pattern is formed after anisotropic wet etching. We compare three textured surface with different morphology (random texture, random pyramids and inverted pyramids) and then different geometry of inverted pyramid arrays in terms of reflectivity.

• 한국진공학회지
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• 제19권2호
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• pp.96-104
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• 2010

NIL, S-FIL과 같은 각인 기술(Imprinting lithography)를 적용하기 위한 투명하고 단단한 복제 틀(replica hard mold)을 제작하여 고가의 원판(master)와 패턴이 형성되는 기판과의 접촉을 근본적으로 방지해 경제적인 공정이 가능함을 제안한다. 실리콘 웨이퍼(Si wafer)와 같은 원판(master)과 패턴 형성 시 사용되는 기판과 직접적인 접촉을 방지하기 위해 우선 액상 공정을 이용하여 비접착성 표면처리된 고분자 복제(polymer copy)를 매개체(carrier)로 단단한 복제 틀을 제작한다. 이렇게 제작된 단단한 복제 틀(replica hard mold)는 유리와 거의 같은 강도와 투명도를 나타내며, 각인 공정(imprinting process)에서 석영 틀, 실리콘 웨이퍼(quartz mold, Si wafer)과 같이 값비싼 원판(master)의 직접 사용을 대체하여 성공적으로 패턴을 구현할 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.13-13
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• 2009

We have investigated the fabrication and properties of bendable PZT film formed on plastic substrates for the application in flexible memory. These devices used the PZT active layer formed on $SiO_2/Si$ wafer by sol-gel method with optimized device layouts and Pt electrodes. After etching Pt/PZT/Pt layers, patterned by photolithography process. these layers were transferred on PET plastic substrate using elastomeric stamp. The level of performance that can be achieved approaches that of traditional PZT. devices on rigid bulk wafers.

• 대한전기학회논문지:시스템및제어부문D
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• 제51권9호
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• pp.423-430
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• 2002

The fabrication and experimentation of multi-channel electrodes which enable detecting and recording of multi-site neuronal signals have been investigated. A multi-channel electrode array was fabricated by depositing 2000${\AA}$ thick Au layer on the 1000${\AA}$ thick Ti adhesion layer on a glass wafer. The metal paths were patterned by wet etching and passivated by depositing a PECVD silicon nitride insulation layer to prevent signals from intermixing or cross-talking. After placing a thin slice of rat cerebellar granule cell in the culture ring located in central portion of the multi-channel electrode plate, a neuronal signal from an electrode which is in contact with the cerebellar granule cell has been detected. It was found that the electrode impedance ranges 200㏀∼1㏁ and the impedance is not changed by cleaning with nitric acid. Also, the impedance is inversely proportion to the exposed electrode area and the cross-talk is negligible when the electrode spacing is bigger than 600$\mu\textrm{m}$. The amplitude and frequency of the measured action potential were 38㎷ and 2㎑, which are typical values. From the experimental results, the fabricated multi-channel electrode array proved to be suitable for multi-site neuronal signal detection for the analysis of a complicated cell network.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.9-9
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• 2011

The transfer of nano-science accomplishments into technology is severely hindered by a lack of understanding of barriers to nanoscale manufacturing. The NSF Center for High-rate Nanomanufacturing (CHN) is developing tools and processes to conduct fast massive directed assembly of nanoscale elements by controlling the forces required to assemble, detach, and transfer nanoelements at high rates and over large areas. The center has developed templates with nanofeatures to direct the assembly of carbon nanotubes and nanoparticles (down to 10 nm) into nanoscale trenches in a short time (in seconds) and over a large area (measured in inches). The center has demonstrated that nanotemplates can be used to pattern conducting polymers and that the patterned polymer can be transferred onto a second polymer substrate. Recently, a fast and highly scalable process for fabricating interconnects from CMOS and other types of interconnects has been developed using metallic nanoparticles. The particles are precisely assembled into the vias from the suspension and then fused in a room temperature process creating nanoscale interconnect. The center has many applications where the technology has been demonstrated. For example, the nonvolatile memory switches using (SWNTs) or molecules assembled on a wafer level. A new biosensor chip (0.02 $mm^2$) capable of detecting multiple biomarkers simultaneously and can be in vitro and in vivo with a detection limit that's 200 times lower than current technology. The center has developed the fundamental science and engineering platform necessary to manufacture a wide array of applications ranging from electronics, energy, and materials to biotechnology.

• Current Photovoltaic Research
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• 제5권2호
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• pp.55-58
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• 2017

We investigated the influences of dielectric thin film coating on the optical characteristics of c-Si wafers with nanocone (NC) arrays using finite-difference time-domain (FDTD) simulations. Dielectric thin films on high-refractive-index surface can lower optical reflection and reflection dips appear at the wavelengths where destructive interference occurs. The optical reflection of the NC arrays was lower than that of the dielectric-coated planar wafer in broad wavelength range. Remarkable antireflection effects of the NC array could be attributed to beneficial roles of the NCs, including the graded refractive index, multiple reflection, diffraction, and Mie resonance. Dielectric thin films modified the optical reflection spectra of the NC arrays, which could not be explained by the interference alone. The optical properties of the dielectric-coated NC arrays were determined by the inherent optical characteristics of the NC arrays.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.131-132
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• 2008

We describe a fabrication method of submicron glass trenches which have embedded metal lines for the future application of nano-scale RF MEMS devices. The glass wafer was etched using two different conditions to identify the relationship between the slope of glass trenches and the slope of photroresist. A self-aligned metal photomask and negative photroresist (PR) slope were used to insert metal lines inside the glass trenches. The PR slope patterned by backside photolithography was affected by the profile of preformed glass trenches. Gold was well fabricated in the $0.7{\mu}m$ wide trench thanks to the negative PR slope. Nano-scale glass trenches with embedded metal lines can be used as a bottom electrode in submicron beam resonators operating with a high resonant frequency.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1186-1190
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• 2003

In this paper, a valveless bubble-actuated fluid micropump was has been developed and its performance was tested. The valveless micropump consists of the lower plate, the middle plate, the upper plate and a resistive heater. The lower plate includes the nozzle-diffuser elements and the double-chamber. Nozzle-diffuser elements and a double-chamber are fabricated on the silicon wafer by the DRIE(Deep Reactive Ion Etching) process. The lower plate also has inlet/outlet channels for fluid flow. The middle plate is made of glass and plays the role of the diaphragm. The chamber in the upper plate is filled with deionized water, and which contacts with the resistive heater. The resistive heater is patterned on a silicon substrate by Ti/Pt sputtering. Three plates and the resister heater are laminated by the aligner and bonded in the anodic bonder. Since the bubble is evaporated and condensed periodically in the chamber, the fluid flows from inlet to outlet with respect to the diffusion effect. In order to avoid backflow, the double chamber system is introduced. Analytical and experimental results show the validity of the developed double-chamber micropump.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1957-1962
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• 2008

As a field of MEMS, micro-heater fabricated by Au is being introduced and developed in recent years. Previous studies about thermal properties of various forms of micro-heater were not sufficient. In this work, numerical and experimental analysis of the heat generation and the temperature distribution of micro-heater packages for 8 different geometric cases were studied. We fabricated a micro-heater package with silicon wafer, on which Cr/Au layer was laminated before 8 geometric forms of micro-heater were patterned. In each cases, temperature distribution was measured with IR thermal camera. According to the experimental results, which show a good agreement with the results analyzed by CFD, it was found that at 0.5W, the temperature of micro-heater chip which contained $20000{\mu}m$-long, serpentine shaped micro-heater was elevated to a relatively high temperature of $78^{\circ}C$ Consequently, we proposed a geometry of micro-heater which has effective thermal characteristics.