• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.581-590
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• 2003

This paper proposes the routing path selection mechanism for source routing-based PtMP (Point-to-Multipoint) call in ATM switching system. Especially, it suggests PtMP routing path selection method that can share the maximum resource prior to the optimal path selection, guarantee the reduction of path calculation time and cycle prevention. The searching for the nearest branch point from destination node to make the maximum share of resource is the purpose of this algorithm. Therefore among neighbor nodes from destination node by back-tracking, this algorithm fixes the node crossing first the node on existing path having the same Call ID as branch node, constructs the optimal PtMP routing path. The optimal node to be selected by back-tracking is selected by the use of Dijkstra algorithm. That is to say, PtMP routing path selection performs the step of cross node selection among neighboring nodes by back-tracking and the step of optimal node selection(optimal path calculation) among neighboring nodes by back-tracking. This technique reduces the process of search of routing information table for path selection and path calculation, also solves the cycle prevention easily during path establishment.

• Convergence Security Journal
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• v.13 no.6
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• pp.3-9
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• 2013

With the rapidly changing information communication environment and development of technologies, the informati on networks are evolved from traditional fixed form to an active variable network that flexible large variety of data can be transferred. To reflect the needs of users, the next generation using DWDM (Dense Wavelength Division M ultiplexing) transmission system and OXC (Optical Cross Connect) form a dynamic network. After that GMPLS (Ge neralized Multi-Protocol Label Switching) can be introduced to dynamically manage and control the Reconfigurable Optical Add-drop Multiplexer (ROADM)/Photonic Cross Connect (PXC) based network. This paper propose a softw are architecture of Path Computation Element (PCE) protocol that has proposed by Internet Engineering Task Force (IETF) to path computation. The functional blocks and Application Programming Interface (API) of the PCE protoco l implementation are also presented.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.432-435
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• 1990

Neural networks are a class of systems that have many simple processors (neurons) which are highly interconnected. The function of each neuron is simple, and the behavior is determined predominately by the set of interconnections. Thus, a neural network is a special form of parallel computer. Although major impetus for using neural networks is that they may be able to "learn" the solution to the problem that they are to solve, we argue that another, perhaps even stronger, impetus is that they provide a framework for designing massively parallel machines. The highly interconnected architecture of switching networks suggests similarities to neural networks. Here, we present switching applications in which neural networks can solve the problems efficiently. We also show that a computational advantage can be gained by using nonuniform time delays in the network.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.77-80
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• 2003

Switching Mode Power Supply(SMPS) is widely used in many industrial fields. Power factor improvement and harmonic reduction technique are very important in SMPS. In this paper, we propose the circuit applied Flying Capacitor Snubber for improving power factor of boost converter on fast switching state. Snubber circuit consists of a inductor, two diodes and a capacitor. The losses of switching are reduced by inserting a snubber inductor in the series path of the boost switch and the rectifier diode to control the di/dt rate of the rectifier during it's turn-off. Prior to actual experiment, the circuit analysis Is implemented by PSPICE simulation.

• Journal of Power Electronics
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• v.9 no.5
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• pp.708-717
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• 2009

In this paper a new zero voltage transition PWM bridgeless PFC is introduced. The auxiliary circuit provides soft switching condition for all semiconductor devices. Also, in the resonant path of the auxiliary circuit, only two semiconductor devices exist. Therefore the resonant conduction losses are low. Furthermore, the auxiliary circuit semiconductor elements consist of only one diode and one switch. The proposed auxiliary circuit is applied to a bridgeless PFC converter to further reduce conduction and switching losses. In this paper, the operating modes of this converter are explained and the resulting ideal and simulation waveforms are shown. The presented experimental results justify the theoretical analysis.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2464-2466
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• 1998

A switch is a component with two or more ports that selectively transmits, redirects, or blocks optical power in a fiber transmission line. Our switch uses rotation mechanism using stepping motor, hence the common optical fiber can scan and allign to one of the arrayed N optical fibers to provide optical path by electronic precise control. The developed switch is consisted of switching module and its control module. The performance parameters of a switching loss and a repeatability are considered very important. We performed the study to reduce the switching loss and improve the repeatability of switch. The switch can be widely used as a test instrument of optical device and of optical cable in factory, also of optical cable monitoring systems.

• Journal of information and communication convergence engineering
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• v.17 no.3
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• pp.221-226
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• 2019

In this work, a transmitter/receiver front-end module (T/R FEM) with an automatic Tx/Rx switching scheme for a 2.4 GHz microwave power transfer is developed for a retro-reflective beamforming scheme. Recently, research on wireless power transfer techniques has moved to wireless charging systems for mobile devices. Retro-reflective beamforming is a good candidate for tracking the spatial position of a mobile device to be charged. In Tx mode, the T/R FEM generates a minimum of 1 W. It also comprises an amplitude and phase monitoring port for transmitting RF power. In Rx mode, it passes an Rx pilot signal from a mobile device to a digital baseband subsystem to recognize the position of the mobile device. The insertion loss of the Rx signal path is 4.5 dB. The Tx and Rx modes are automatically switched by detecting the Tx input power. This T/R FEM is a design example of T/R FEMs for wireless charging systems based on a retro-reflective beamforming scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• Convergence Security Journal
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• v.13 no.4
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• pp.19-25
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• 2013

The increasing demand for fast, flexible and guaranteed Quality of Service (QoS) in core networks has caused to deploy MultiProtocol Label Switching (MPLS) and Generalized MPLS (GMPLS) control plane. In GMPLS control plane, path computation and cooperation processes are one of the crucial element to maintain an acceptable level of service. The Internet Engineering Task Force (IETF) has proposed the Path Computation Element (PCE) architecture. The PCE is a dedicated network element devoted to path computation process and communications between Path Computation Clients (PCC) and PCEs is realized through the PCE Protocol (PCEP). This paper examines the PCE-based path computation architecture to include the design and implementation of PCEP. The functional modules including Finite State Machine (FSM) and related key design issues of each state are presented. In particular we also discuss internal/external protocol interfaces that efficiently control the communication channels.

• Journal of Power Electronics
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• v.7 no.4
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• pp.278-285
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• 2007

Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.