• ETRI Journal
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• 제27권5호
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• ETRI Journal
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• 제29권3호
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• pp.381-389
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• 2007

In this paper we propose a graph-theoretic method based on linear congruence for constructing low-density parity check (LDPC) codes. In this method, we design a connection graph with three kinds of special paths to ensure that the Tanner graph of the parity check matrix mapped from the connection graph is without short cycles. The new construction method results in a class of (3, ${\rho}$)-regular quasi-cyclic LDPC codes with a girth of 12. Based on the structure of the parity check matrix, the lower bound on the minimum distance of the codes is found. The simulation studies of several proposed LDPC codes demonstrate powerful bit-error-rate performance with iterative decoding in additive white Gaussian noise channels.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• Journal of Communications and Networks
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• 제13권3호
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

• Nuclear Engineering and Technology
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• 제32권6호
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• pp.605-617
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• 2000

Nodal transport methods are studied for the solution of two dimensional discrete-ordinates, simplified even-parity transport equation(SEP) which is known to be an approximation to the true transport equation. The polynomial expansion nodal method(PEN) and the analytic function expansion nodal method(AFEN）which have been developed for the diffusion theory are used for the solution of the discrete-ordinates form of SEP equation. Our study shows that while the PEN method in diffusion theory can directly be converted without complication, the AFEN method requires a theoretical modification due to the nonhomogeneous property of the transport equation. The numerical results show that the proposed two methods work well with the SEP transport equation with higher accuracies compared with the conventional finite difference method.

• 전기학회논문지
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• 제61권1호
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• pp.16-21
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• 2012

The growth in IT industry has brought a corresponding rise in the number of connected digital devices in the distribution network. These digital loads lead to AC to DC conversion losses in order to supply power to them. The more the renewable energies and plug-in electrical vehicles penetrated our lives, the more the electrical losses are caused by AC to DC conversion process. Hence, this paper suggests the methodology for evaluating the amount of power supplied according to the ratio of DC power supply and performs an economic analysis of DC distribution system considering grid parity. In here, the cost of carbon emission reduced by renewable energy is also concerned.

• International Journal of Computer Science & Network Security
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• 제22권2호
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• pp.369-375
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• 2022

The article is timed to coincide with the thirtieth anniversary of Ukraine's independence. Based on the generalization of fundamental and applied studies of scientists, the author's vision of such category as the gender parity is conceptualized. Based on the analysis of historical events related to the development of the state, the formation of cultural and social values in determining the gender identity of modern society is substantiated. Based on the analysis of literary and regulatory sources, the structure of the state administration of Ukraine is visualized, which has become the basis for the diagnosis of gender aspects. Based on the analysis, the problems of gender parity in the public administration system of Ukraine are identified.

• Journal of applied mathematics & informatics
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• 제7권2호
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• pp.597-603
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• 2000

In this paper, we deal with the European Asian Arithmetical option and find the unique rational price associated with option and Asian arithmetical call-put parity.

• Asian-Australasian Journal of Animal Sciences
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• 제16권11호
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• pp.1555-1559
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• 2003

The objective of the present study was to explore associations between five microsatellites linked to $Fec^B$ and $FecX^I$ genes and litter size in Small Tail Han sheep. The polymorphisms of five microsatellite loci, OarAE101, BM1329, BMS2508, TGLA54 and TGLA68 were detected in 244 ewes of Small Tail Han sheep. Analysis of association between three microsatellite loci (BMS2508, BM1329 and OarAE101) located in the 10 cM region covering the $Fec^B$ gene (Booroola gene) and litter size in Small Tail Han sheep indicated that BMS2508 had significant effect on litter size in the second parity (p<0.05), but no significant effect on litter size in the first parity (p>0.05), while the other two microsatellite loci had no significant effect on litter size in both the first and the second parity in Small Tail Han sheep (p>0.05). At microsatellite locus BMS2508, least squares means in the second parity of genotypes 101/111 and 99/109 were significantly higher than those of genotypes 99/99, 99/101, 99/111 and 99/115 (p<0.05); least squares mean in the second parity of genotype 101/111 was significantly higher than that of genotypes 109/111 and 111/111 (p<0.05). Results of this study also indicated that two microsatellite loci (TGLA54 and TGLA68) that confined the 28.7 cM region covering the $FecX^I$ gene (Inverdale gene) did not affect litter size in both the first and the second parity in Small Tail Han sheep significantly (p>0.05). The information found in the present study is very important for improving the reproductive performance in sheep breeds by marker assisted selection.

• 대한전자공학회논문지SD
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• 제43권7호
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• pp.50-57
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• 2006

Low-density parity check (LDPC) code는 최근 그 우수한 성능으로 인하여 4세대 무선 이동 통신용 채널 코딩으로 주목받고 있고 유럽의 고화질 위성방송 규격으로 채택되었다. 그러나 기존의 연구들이 제안한 parity check matrix (H-matrix)는 실제로 하드웨어로 구현함에 있어서 인코더 혹은 디코더에 제약을 가지고 있다. 이러한 문제점을 해결하고자 본 논문에서는 인코더와 디코더 양쪽 모두 효율적으로 하드웨어로 구현이 가능한 hybrid H-matrix 구조를 제안한다. Hybrid H-matrix는 semi-random 방식과 partly parallel 방식을 결합하여 하드웨어로 구현시 partly parallel 방식이 가지는 디코더의 복잡도가 감소되는 장점을 유지하면서 인코더 또한 semi-random 방식을 사용하여 복잡도가 감소된다. 제안한 구조를 사용하여 LDPC 인코더와 디코더를 설계하고 합성하여 기존의 결과와 비교하였다.