• Journal of Electrical Engineering and Technology
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• 제8권1호
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• pp.168-175
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• 2013

This paper presents compact dual-band WLAN filter and filter module. They were developed by embedding all of the passive lumped elements into a LTCC substrate. In order to reduce the size/volume of the filter and avoid EM parasitic couplings between the passive elements, the proposed filter was designed using a 3rd order Chebyshev circuit topology and J-inverter transformation technology. The 3rd order Chebyshev bandpass filter was firstly designed for the band-selection of the 802.11b and was then transformed using finite transmission zeros technologies. Finally, the dual-band filter was realized by adding two notch resonators to the 802.11b filter circuit for the band-selection of the 802.11a/g. The maximum insertion losses in the lower and higher passbands were better than 2.0 and 1.3 dB with minimum return losses of 15 and 14 dB, respectively. Furthermore, the filter was integrated with a diplexer to clearly split the signals between 2 and 5 GHz. The maximum insertion and minimum return losses of the fabricated module were 2.2 and 14 dB at 2.4 - 2.5 GHz, and 1.6 and 19 dB at 5.15 - 5.85 GHz, respectively. The overall volume of the fabricated filter was $2.7{\times}2.3{\times}0.59mm^3$.

• 한국전자파학회논문지
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• 제13권6호
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• pp.528-537
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• 2002

본 논문에서는 능동소자를 포함하는 마이크로파 회로의 주파수 특성을 해석하기 위하여 확장된 유한차분 시간영역법 (FDTD) 을 이용했다. R, L, C와 같은 집중소자가 전송선로에 삽입된 FDTD 집중소자 모델링을 통해 하이브리드 회로 해석에 대한 기초 연구를 수행하였고, 네트워크 모델링을 이용하여 기생 커패시턴스와 인덕턴스의 값을 추출함으로써 보다 정확한 기생, 방사, 결합까지 고려하는 FDTD만의 고유한 주파수 응답을 확인할 수 있었다. 또한 FDTD를 이용하여 모델링된 다이오드를 사용한 평형 혼합기를 설계하여 상용 회로 시뮬레이터보다 정확하고 실제적인 회로의 주파수 응답을 획득하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.801-803
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• 2004

The current drive in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure playa significant role and degrade the device performance. These other resistances need to be less than $10{\%}-20{\%}$ of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• 반도체디스플레이기술학회지
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• 제2권2호
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• pp.17-20
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• 2003

The current drive in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure playa significant role and degrade the device performance. These other resistances need to be less than 10%-20% of the channel resistance. To achieve the requirements, we should investigate a methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2010년도 하계학술대회 논문집
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• pp.37-38
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• 2010

For MHz-class high frequency inverter in wireless power transfer applications, the voltage/current surges can be occurred in power stage when driving on the inverter. And also, the high-frequency oscillations can be produced at a high switching frequency due to the parasitic elements. The voltage and current stresses of the switching devices lead to the switching losses. The efficiency of the high frequency inverter will be reduced. And the inverter circuit with the sudden voltage and current fluctuations also generates the noise such as the EMI. Zero voltage, zero current switching technique can be used to reduce the switching loss and the noise. The high power density and high efficiency can be obtained. In this paper, the high-frequency inverter for short-range wireless power transfer applications was discussed. The feasible inverter circuit is analyzed in the circuit operating characteristics and the results are verified by the simulation.

• 한국정밀공학회지
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• 제20권2호
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• pp.168-175
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• 2003

In this research, a bridge-type flexure hinge mechanism is developed and optimized to amplify the displacement of a multilayer piezostack. Developed hinge mechanism has three-dimensional structure to reduce link size, so it have high amplification ratio with respect to small size. A flexure hinge is assumed to be 6 degree-of-freedom spring elements and matrix methods are used to model a hinge mechanism. To verify derived matrix model, a displacement and frequency experiments are performed. The analysis result shows that the displacemental error between matrix model and experiments is below 10 percents and the deformation of hinge in parasitic direction should be considered In hinge modeling. Using developed matrix model, an optimal design is performed to maximize the performance of hinge mechanism.

• 대한전기학회논문지
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• 제43권3호
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• pp.409-419
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• 1994

This paper deals with the design criteria and conduction noise reduction of electronic ballast system which is based on half-bridge series inverters. The system is theoretically analyzed in six modes and operating frequency range is selected to obtain the high efficacy and no sound noise. It is proposed the criteria for determining the values of L and C which are the dey points in system design Because of high operating frequency, electromagnetic noise, especially conduction noise, is a serious problem in electronic ballasts. To reduce the conduction noise, the operation and attenuation characteristics of noise filter are analyzed and the method to determine the values of filter elements is proposed. Also, the parasitic components of the inductor and capacitor are taken into consideration in filter analysis. Digital simulations and experiments are carried out to prove the theoretical results. And perfor mances of the system are verified through tests.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.135-136
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• 2006

In this paper, isolation strategies for improving broadband circuit performance and preventing noise arising from circuit component coupling are presented. Equivalent circuit parameters, including parasitic elements, are determined for capacitor and inductor structures. The effects of the relative position of the components with regard to a ground plane are considered in the equivalent circuits. Novel meshed ground structures are investigated to determine a configuration that improves the overall circuit performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.559-562
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• 2000

The problem of noise generation due to PWM switched-mode power converter has been widely noticed from the viewpoint of Electromagnetic Interference(EMI). Many kings of topologies for resonant converters have been developed both to overcome this noise problem and to attain high power efficiency. It is reported in references that resonant converters which are derived from PWM converter using resonant switch show much lower noise characteristics than PWM converter, and that current-mode resonant converter is more sensitive to stored charge in rectifying diode than voltage-mode counterpart concerning surge generation at diode’s turn-off. On the other hand, above mentioned resonant converters have defect of high-voltage stress on semiconductor switch and complicated circuit configuration. Hence, the simplified Forward-type resonant converter has been proposed and investigated due to its prominent features of simplicity of circuit configuration, low voltage stress and high stability. However, its noise characteristics still remain unknown. The purpose of this paper is to study quantitatively the noise characteristics of this simplified Forward-type resonant converter by experiment and analysis. The influence of parasitic elements and stored charge in rectifying diode on noise generation has been clarified.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.557-560
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• 1999

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the parasitic capacitive elements present in a pixel. The capacitive coupling of the data line signal onto the pixel causes a pixel voltage error. In this study semi-empirical capacitance model which is adopted from VLSI interconnection capacitance calculations was used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and given image pattern, the root mean square(RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained from this study could be utilized to design the larger area and finer image quality panel.