• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.899-903
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• 2003

In this paper, a wide band helical antenna for mobile handset using parasitic element effect has been investigated. To obtain the effect of parasitic element, we utilized the cylindrical conductor which is not feed. As thickness of cylindrical conductor is increasing, second and third resonance frequency become abruptly variable. In case of that 4.5mm diameter parasitic element cylindrical conductor is inserted, normal mode helical antenna obtained bandwidth of around 900 MHz on the limit of R. L., - 5 dB.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.2
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• pp.1-9
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• 1997

For the reduction of parasitic inductance and matching of bonding wire in the package of microwave devices, we propose multiple bonding wires buried in a dielectric material of FR-4 composite. This structure is analyzed using the method of moments (MoM) and compared with the common bondwires and ribbon interconnections. The FR-4 composite is modelled by the cole-cole model which can consider the loss and the variation of the permittivity in a frequency. At 20 GHz, the parasitic reactance is reduced by 90%, 80%, 60% compared to those of a single bonding wire in air, double bonding wires in air and ribbon interconnection in air, respectively. Also, the new bondwire shows very good matching of 60.ohm characteristic impedance and has 15dB, 10dB, 5dB improvement of the return loss and 2.5dB, 0.7dB, 0.2dB improvement of the insertion loss compared to the common interconnections. This technique can minimize the parasitic effect of bondwires in microwave device packaging.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.485-490
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• 2010

We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.

• Parasites, Hosts and Diseases
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• v.58 no.2
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• pp.195-200
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• 2020

Soil-transmitted helminths, including Ascaris lumbricoides and Trichuris trichiura, are important intestinal parasites mostly affecting younger people in developing countries. In 2014-2015, we performed mass fecal examinations targeting a total of 2,227 schoolchildren in 3 districts (South Dagon, North Dagon, and Hlaing-thar-yar) of Yangon Region, Myanmar, using the Kato-Katz thick smear technique. The egg positive children were subjected to a mass drug administration (MDA) using a single oral dose of 400 mg albendazole. The pre-treatment egg positive rate (EPG/person) of A. lumbricoides averaged 17.2% (15,532); it was 25.2% (21,796), 14.2% (11,816), and 12.8% (12,983) in 3 districts, respectively, and that of T. trichiura averaged 19.4% (1,074), and was 24.1% (1,040), 12.3% (852), and 21.2% (1,330) in 3 districts, respectively. Follow-up fecal examinations performed 4 months post-MDA revealed considerable decreases of A. lumbricoides prevalence (EPG/person) to av. 8.3% (12,429), and 13.7% (17,640), 8.0% (7,797), and 4.5% (11,849) in 3 districts, respectively. However, T. trichiura did not show any recognizable decrease in the prevalence (EPG/person) remaining at av. 18.2% (862), and 18.5% (888), 11.5% (812), and 23.3% (887) in 3 districts, respectively. The results demonstrated difficulty in short-term control of T. trichiura by MDA using albendazole and suggested necessity of either a long-term MDA (>10 years) or changing the albendazole regimen into 2~3-day course (total 800 or 1,200 mg), or using an alternative drug/drug combination.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.250-256
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• 2007

We analyzed the effect of a pixel and all the inter-electrode capacitances in a unit pixel of TFT-LCDs on the gray scale capability. The pixel and all the inter-electrode parasitic capacitances were obtained from the tree dimensional profiles of potential distribution and molecular director considering lateral fields generated at the edge of the pixel. To obtain the RMS and kickback voltages of the pixel, we constructed an equivalent circuit of the panel containing all the parasitic capacitances. The calculation was performed though H-SPICE. As results, we confirmed that the pixel becomes smaller, the effect of parasitic capacitances on the gray scale capability becomes larger.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.155-156
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• 2007

A wideband monopole antenna using a parasitic branch is proposed for allowing operations at multiple frequency bands specified in GSM($824{\sim}894MHz$), PCS($1750{\sim}1870MHz$), WiBro($2.3{\sim}2.4GHz$), WLAN/ISM ($2.4{\sim}2.48GHz$) and SDMB($2.605{\sim}2.655GHz$). We have used two branch monopoles and the one parasitic branch. Prototype of the multiband antenna have been successfully implemented and good radiation characteristics the operating frequency bands have been obtained. The effect of a parasitic branch was also studied.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.11-18
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• 1997

By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.