• Journal of Power Electronics
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• v.15 no.4
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• pp.1035-1046
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• 2015

This study presents a practical implementation of a multi-mode two-phase interleaved boost converter for fuel cell electric vehicle application. The main operating modes, which include two continuous conducting modes and four discontinuous conducting modes, are discussed. The boundaries and transitions among these modes are analyzed with consideration of the inductor parasitic resistance. The safe operational area is analyzed through a comparison of the different operating modes. The output voltage and power characteristics with open-loop or closed-loop operation are also discussed. Key performance parameters, including the DC voltage gain, input ripple current, output ripple voltage, and switch stresses, are presented and supported by simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.592-593
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• 2012

Buck converter must operate at fairly high switching frequency for miniaturizing a whole circuit and achieving a fast response. However, at the conditions of low output voltage, high output current, and high switching frequency, the influence of parasitic elements to circuit operation will become extremely obvious. In this paper, it has been shown that these parasitic elements of output capacitor link the ripple of the output voltage. The MCP capacitors and aluminum electrolytic capacitors are applied to the buck converter and observed characteristics and the experimental results were reported.

• Journal of the Korean Magnetics Society
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• v.5 no.5
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• pp.828-832
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• 1995

This paper describes the efficient design, analysis method and experimental verification of capacitor discharge impulse magnetizer system. A capacitor discharge magnetizer system is used to produce a high current impulse of short duration in this magnetizing fixture. The parasitic resistance and parasitic inductance of the capacitor discharge impulse magnetizer system have been estimated using known air-core test coil. Finite element analysis (using MAXWELL 2-D field simulator) and magnetizing circuit analysis (using SPICE) are also used as part of the design and analysis process of the capacitor discharge impulse magnetizer system. Application study for a magnetizing fixture design is shown. 8-pole magnetizing fixture has been designed and analyzed using finite element analysis. The fixture design for 8-pole magnet are presented along with the experimental results. The experimental results have been achieved using a high-voltage, high-energy capacitor discharge impulse magnetizer and 8-pole iron core fixtures (charging voltage : 2000[V], capacitor bank : 4000[$\mu\textrm{F}$]).

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.89-92
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• 2001

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.134-141
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• 2022

This study presents a method for reducing current distortion that occurs when a dual-buck inverter generates reactive power. Dual-buck inverters, which are only capable of unity power factor operation, can generate reactive power capabilities by modifying a modulation technique. However, under non-unity power factor conditions, current distortion occurs at zero-crossing points of grid voltage and output current. This distortion is caused by parasitic capacitors, dead-time, and discontinuous conduction mode operation. This study proposes a modified modulation method to alleviate the current distortion at zero-crossing point of the grid voltage. A repetitive controller is applied to reduce this distortion of the output current. A 1 kVA prototype is built and tested. Simulation and experimental results demonstrate the effectiveness of the proposed method.

• Current Optics and Photonics
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• v.4 no.5
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• pp.434-440
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• 2020

Based on single-mode rate equations, we present an improved equivalent-circuit model for distributed-feedback (DFB) lasers that accounts for the effects of parasitic parameters and nonradiative recombination. This equivalent-circuit model is composed of a parasitic circuit, an electrical circuit, an optical circuit, and a phase circuit, modeling the circuit equations transformed from the rate equations. The validity of the proposed circuit model is verified by comparing simulation results to measured results. The results show that the slope efficiency and threshold current of the model are 0.22 W/A and 13 mA respectively. It is also shown that increasing bias current results in the increase of the relaxation-oscillation frequency. Moreover, we show that the larger the bias current, the lower the frequency chirp, increasing the possibility of extending the transmission distance of an optical-fiber communication system. The results indicate that the proposed circuit model can accurately predict a DFB laser's static and dynamic characteristics.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2273-2277
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• 2010

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.215-218
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• 2009

In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.3
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• pp.183-189
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• 2010

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.37-38
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• 2010

For MHz-class high frequency inverter in wireless power transfer applications, the voltage/current surges can be occurred in power stage when driving on the inverter. And also, the high-frequency oscillations can be produced at a high switching frequency due to the parasitic elements. The voltage and current stresses of the switching devices lead to the switching losses. The efficiency of the high frequency inverter will be reduced. And the inverter circuit with the sudden voltage and current fluctuations also generates the noise such as the EMI. Zero voltage, zero current switching technique can be used to reduce the switching loss and the noise. The high power density and high efficiency can be obtained. In this paper, the high-frequency inverter for short-range wireless power transfer applications was discussed. The feasible inverter circuit is analyzed in the circuit operating characteristics and the results are verified by the simulation.