• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.25-28
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• 2000

A capacitance-type humidity sensors in which porous silicon layer is used as humidity-sensing material was developed. This sensors was fabricated monolithically to be compatible with the typical IC process technology except for the formation of porous silicon layer. As the sensors is made as a mesa structure, the correct measurement of capacitance is expected because it can remove the effect of the parasitic capacitance from the bottom layer and another junctions. To do this, the sensor was fabricated using process steps such as localized formation of porous silicon, oxidation of porous silicon layer and etching of oxidized porous silicon layer. From completed sensors, capacitance response was measured on the relative humidity of 25 to 95% at room temperature. As the result the measured capacitance showed the increase over 300% at the low frequency of 120Hz, and showed little dependence on the temperature between 10 to $40^{\circ}C$.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1326-1335
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• 2019

Common mode (CM) chokes are a crucial part in EMI filters for mitigating the electromagnetic interference (EMI) of switched-mode power supplies (SMPS) and for meeting electromagnetic compatibility standards. However, the parasitic capacitances of a CM choke deteriorate its high frequency filtering performance, which results in increases in the design cycle and cost of EMI filters. Therefore, this paper introduces a negative capacitance generated by a negative impedance converter (NIC) to cancel the influence of equivalent parallel capacitance (EPC). In this paper, based on a CM choke equivalent circuit, the EPCs of CM choke windings are accurately calculated by measuring their impedance. The negative capacitance is designed quantitatively and the EPC cancellation mechanisms are analyzed. The impedance of the CM choke in parallel with negative capacitances is tested and compared with the original CM choke using an impedance analyzer. Moreover, a CL type CM filter is added to a fabricated NIC prototype, and the insertion loss of the prototype is measured to verify the cancellation effect. The prototype is applied to a power converter to test the CM conducted noise. Both small signal and EMI measurement results show that the proposed technique can effectively cancel the EPCs and improve the CM filter's high frequency filtering performance.

• Journal of Sensor Science and Technology
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• v.21 no.3
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• pp.235-239
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• 2012

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.

• Journal of electromagnetic engineering and science
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• v.12 no.2
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• pp.185-188
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• 2012

A compact monopole antenna possessing triple resonance ($f_1$, $f_2$, $f_3$) characteristics for (USB) dongle applications is presented. The resonance characteristic $f_1$ is determined by the overall length of the antenna. The monopole antenna acts as the main radiator for $f_3$ as well as the coupling feeding structure for the parasitic resonators in $f_1$, $f_2$. The resonance characteristic $f_2$ is achieved by a combination of the capacitance formed by the coupling between the top and bottom parasitic substrate resonators and the inductance generated by a via bridging the two parasitic resonators.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.936-939
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• 2005

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.356-359
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• 2007

Writable Cholesteric Liquid Crystal Display and the algorithm used to detect its image were developed. We could use any hard tip, ex: the tip of a forefinger, to directly write an image on the surface of Cholesteric Liquid Crystal Display (CHLCD). By measuring the capacitance of one pixel of test cell (12mm x 15mm/1x1), F-state or P-state could be detected. By measuring the capacitance of one pixel of 4.1" CHLCD (241um x 241um/ 320x320), F-state or Pstate could not be detected, due to the effect of parasitic capacitance. Therefore, high frequency measurement and the algorithm were developed to detect the image on CHLCD.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.129-133
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• 1997

A circuit model for a field emission triode has been proposed. The model parameters have been extracted from he fabricated silicon tip array and verified by comparing with the results simulated by circuit simulator(SPICE). The cut-off frequency can be calculated from the parametric capacitance and the transconductance values extracted from measurements. For the field emission triode, the capacitance of 3.45fF/tip and the transconductance of 0.94nS/tip have been measured under the emission current of 4.1nA/tip. From these values, the cut-off frequency is predicted to be 43 kHz but th measured one came out to be 6 kHz. because o the parasitic capacitance components.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.3
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• pp.529-536
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• 2001

We investigate a surface-micromachined capacitive accelerometer with the grid-type electrodes surrounded by a perforated proof-mass frame. An electromechanical analysis of the microaccelerometer has been performed to obtain analytical formulae for natural frequency and output sensitivity response estimation. A set of prototype devices has been designed and fabricated based on a 4-mask surface-micromachining process. The resonant frequency of 5.8$\pm$0.17kHz and the detection sensitivity of 0.28$\pm$0.03mV/g have been measured from the fabricated devices. The parasitic capacitance of the detection circuit with a charge amplifier has been measured as 3.34$\pm$1.16pF. From the uncertainty analysis, we find that the major uncertainty in the natural frequency of the accelerometer comes from the micromachining error in the beam width patterning process. The major source of the sensitivity uncertainty includes uncertainty of the parasitic capacitance, the inter-electrode gap and the resonant frequency, contributing to the overall sensitivity uncertainty in the portions of 75%, 14% and 11%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.