• 전기학회논문지P
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• 제54권4호
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• pp.163-170
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• 2005

This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

• 전자공학회논문지B
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• 제32B권3호
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• pp.11-23
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• 1995

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.735-738
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• 2008

A 6 D.O.F Stewart platform type parallel robot has been developed as a simulator to test the surveillance robot stabilization control. Since the surveillance robot is installed on the unmanned ground vehicle (UGV), it is required to have a stabilization control system to compensate the disturbance from the UGV. PID control scheme has been applied to the parallel robot to generate controlled motion following the input motion.

• 한국기계가공학회지
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• 제8권4호
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• pp.41-47
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• 2009

This research deals with evaluation of machining accuracy for Parallel Kinematic Machine Tool(PKMT) applied parallel type robot system with high precision and stiffness. For this purpose, machine simulation is carried out to foreknow collision and interference between workpiece and tool. Furthermore, on the basis of machine simulation data, PKMT is manufactured. Machining accuracy such as cylindricity straightness, squareness, parallelism circularity, concentricity pitch error and yaw error, is measured by using coordinate measuring machine. Test piece for evaluation of machining accuracy is designed and manufactured under the standard of ISO 10791-7.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.327-331
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• 2008

This paper dealt with high speed breaking method to parallel arcing in low-voltage systems. The proposed high speed breaking circuit consists of a Rogowski coil and an integrator, and operates with an earth leakage circuit breaker (ELCB). A parallel arcing state was simulated by a short circuit using stripped wires. In this test, we analyzed tripping characteristics of the circuit breaker by the length of wires from 5m to 30m. From the experimental results, we confirmed that the proposed method can break the parallel arcing within a few millisecond.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• 전자공학회논문지C
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• 제34C권6호
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• pp.44-50
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• 1997

This paper describes the design and test of an on-line non-invasive network performance monitor (hardware portion) for the SPAX parallel computer. The SPAX parallel computer supports up to 256 intel P6 processors with 4 P6 processors constituting a processign node. The nodes are interconnected with a dual two-level crossbar network calle dXcent-net. Since the performance of the SPAX parallel computer is highly dependent on the proper and efficient operation of the network, an on-line non-invasive network performance monitor (with hardware components) has been developed to aid in the monitoring and tunign of the Xcent-net. Successful testing of a prototype node monitor board and PC interface system shows that our monitor design provides a low-cost practical solution to this problem.

• Journal of Power Electronics
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• 제15권1호
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• pp.116-122
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• 2015

This paper presents a new current sharing control strategy for parallel-connected, synchronised three-phase DC-AC converters employing space vector pulse width modulation (SVPWM) without current sharing reactors. Unlike conventional control methods, the proposed method breaks the paths of the circulating current by dividing the switching cycle evenly between parallel connected equally rated converters. Accordingly, any inter-module reactors or circulating current control will be redundant, leading to reductions in system costs, size, and control algorithm complexity. Each converter in the new scheme employs a synchronous dq current regulator that uses only local information to attain a desired converter current. A stability analysis of the current controller is included together with a simulation of the converter and load current waveforms. Experimental results from a 2.5kVA test rig are included to verify the proposed control method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.444-447
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• 2004

A heart diagnosis system adopts hundreds of Superconducting Quantum Interface Device(SQUID) sensors for precision MCG(Magnetocardiogram) or MEG(Magnetoencephalogram) signal acquisitions. This system requires correct and real-time data acquisition from the sensors in a required sampling interval, i.e., 1 mili-second. This paper presents our hardware design and test results, to acquire data from 256 channel analog signal with 1-ksample/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, and 8-bit microprocessors. We chose to implement parallel data transfer between microprocessors as an effective way of achieving such data collection. Our result concludes that the data collection can be done in 250 ${\mu}sec$ time-interval.

• International Journal of Air-Conditioning and Refrigeration
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• 제16권2호
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• pp.37-43
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• 2008

The air and water flow distributions are experimentally studied for a round header - ten flat tube configuration. Three different inlet orientation modes (parallel, normal, vertical) were investigated. Tests were conducted with downward flow configuration for the mass flux from 70 to $130kg/m^2s$, quality from 0.2 to 0.6, non-dimensional protrusion depth (h/D) from 0,0 to 0.5. It is shown that, for almost all the test conditions, vertical inlet yielded the best flow distribution, followed by normal and parallel inlet. Possible explanation is provided using flow visualization results.