• Title/Summary/Keyword: parallel test

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Performance Characterization of Tachyon Supercomputer using Hybrid Multi-zone NAS Parallel Benchmarks (하이브리드 병렬 프로그램을 이용한 타키온 슈퍼컴퓨터의 성능)

  • Park, Nam-Kyu;Jeong, Yoon-Su;Yi, Hong-Suk
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.138-144
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    • 2010
  • Tachyon primary system which introduces recently is a high performance supercomputer that composed with AMD Barcelona nodes. In this paper, we will verify the performance and parallel scalability of TachyonIn by using multi-zone NAS Parallel Benchmark(NPB) which is one of a program with hybrid parallel method. To test performance of hybrid parallel execution, B and C classes of BT-MZ in NPB version 3.3 were used. And the parallel scalability test has finished with Tachyon's 1024 processes. It is the first time in Korea to get a result of hybrid parallel computing calculation using more than 1024 processes. Hybrid parallel method in high performance computing system with multi-core technology like Tachyon describes that it can be very efficient and useful parallel performance benchmarks.

Equal Current Distribution in Superconducting Parallel Circuits Using Multi-Interphase Transformers (선로간 변압기를 이용한 초전도 병렬회로의 평형 전류분배)

  • Hyun, Ok-Bae;Choi, Yong-Sun;Sim, Jung-Wook;Kim, Hye-Rim;Hwang, Si-Dole
    • Proceedings of the KIEE Conference
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    • 2003.04a
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    • pp.140-142
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    • 2003
  • Small impedances in the superconducting Parallel circuits cause unequal distribution of the currents in the circuits. This results in Quenches or losses in some superconducting parts. This paper presents the fabrication and test results of a multi-interphase transformers (IPT) for equal current distribution in parallel circuits. Test results show that the IPT can effectively make the current distribution uniform in parallel circuits that have unequal resistances.

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Analysis of Stator-Rotor Interactions by using Parallel Computer (정익-동익 상호작용의 병렬처리해석)

  • Lee J. J.;Choi J. M.;Lee D. H.
    • 한국전산유체공학회:학술대회논문집
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    • 2004.10a
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    • pp.111-114
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    • 2004
  • CFD code that simulates stator-rotor interactions is developed applying parallel computing method. Modified Multi-Block Grid System which enhances perpendicularity in grid and is appropriate in parallel processing is introduced and Patched Algorithm is applied in sliding interface which is caused by movement of rotor. The experimental model in the turbo-machine is composed of 11 stators and 14 rotors. Analyses on two test cases which are one stator - one rotor model and three stators - four rotors model are performed. The results of the two cases have been compared with the experimental test data.

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Pattern Classification with the Analog Cellular Parallel Processing Networks (아날로그 셀룰라 병렬 처리 회로망(CPPN)을 이용한 Pattern Classification)

  • 오태완;이혜정;김형석
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2367-2370
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    • 2003
  • A fast pattern classification algorithm with Cellular Parallel Processing Network-based dynamic programming is proposed. The Cellular Parallel Processing Networks is an analog parallel processing architecture and the dynamic programming is an efficient computation algorithm for optimization problem. Combining merits of these two technologies, fast Pattern classification with optimization is formed. On such CPPN-based dynamic programming, if exemplars and test patterns are presented as the goals and the start positions, respectively, the optimal paths from test patterns to their closest exemplars are found. Such paths are utilized as aggregating keys for the classification. The pattern classification is performed well regardless of degree of the nonlinearity in class borders.

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Design and Fabrication of Parallel Wounded HTS Transformer Windings with Transpositions (전위를 고려한 고온초전도 변압기용 병렬권선의 설계 및 제작)

  • 김우석;김성훈;최경달;주형길;홍계원;한진호;박정호;송희석;한송엽
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.02a
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    • pp.203-205
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    • 2003
  • Parallel wounded windings with BSCCO-2223 HTS tape for 1MVA HTS transformer were designed and prototype windings were fabricated in double pancake type. The parallel HTS tapes were transposed between the pancakes via non-superconducting joints because it is hard to make transpositions inside the pancake windings. The prototypes were wound using copper tape with same size as BSCCO-2223 tape, which will be used in 1MVA HTS transformer. The windings will be used for high voltage test and insulation test of the transformer Parallel HTS windings are going to be fabricated and tested for current distribution in near future.

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Equal Current Distribution in Parallel Resistive SFCL Using SIPT (SIPT를 이용한 병렬 저항형 한류기의 평형전류분배)

  • 심정욱;최용선;김혜림;현옥배
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.10a
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    • pp.109-112
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    • 2003
  • Small impedances in the superconducting parallel circuits cause unequal distribution of the currents in the circuits. This results in quenches or losses in some superconducting parts and decrease of total transport current. This paper presents the fabrication and test results of a superconducting multi- interphase transformers (SIPT) for equal current distribution in superconducting parallel circuits. The secondary loop configuration with air core SIPT seems to be the most efficient one for the SFCL. Test results show that the SIPT can effectively make the current distribution uniform in Parallel circuits that have unequal resistances.

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An Efficient Parallel Testing using The Exhaustive Test Method (Exhaustive 테스트 기법을 사용한 효율적 병렬테스팅)

  • 김우완
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.3_4
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    • pp.186-193
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    • 2003
  • In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

A Study on the Built-in Test Circuit Design for Parallel Testing of CAM(Content Addressable Memory) (CAM(Content Addressable Memory)의 병렬테스팅을 위한 Built-in 테스트회로 설계에 관한 연구)

  • 조현묵;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1038-1045
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    • 1994
  • In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.

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A Study on the Extension of TTCN using Object-Oriented Model (객체 지향 모형을 이용한 TTCN 확장에 관한 연구)

  • 최준규;송주석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.12
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    • pp.1423-1434
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    • 1991
  • This paper extends TTCN, a conformance test notation, using object oriented concepts including object, class and inheritance. In distributed system environments, since test systems that should test the implementations for application protocols whether they conform to the standard protocol include protocol test behaviours executed in parallel, the converntional TTCN can't describe whole thest suites explicitly. ISO is working the extension of TTCN including parallel notations, but concurrently if TTCN could be applied by the object model that regards a parallel test component as a object, we would gain the advantages of reliability and software reusability, and make TTCN a test language.

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Test Time Reduction for BIST by Parallel Divide-and-Conquer Method (분할 및 병렬 처리 방법에 의한 BIST의 테스트 시간 감소)

  • Choe, Byeong-Gu;Kim, Dong-Uk
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.6
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    • pp.322-329
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    • 2000
  • BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

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