• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.397-403
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• 2015

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.6
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• pp.287-292
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• 2001

This paper deals with the configuration, operating principles, systematic calculation method of parameter and optimization method of test circuit for parallel current injection method, series voltage injection method and hybrid synthetic test method as the method for performance test of circuit breaker with extra high interrupting capacity. The test method depicted above is applied to short-circuit making and breaking test (operating sequence :Os CdOs, Od-CdOs) and out-of-phase tests(operating sequence :Os, CdOs) for performance test of the newly-developed 420kV, 50kA and 800kV 50kV puffer-type gas circuit-breaker according to IEC 60056 and IEC 60427. The testing results, evaluation of equivalence for test and analyzed results are also presented in this paper.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.4
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• pp.16-25
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• 2003

A parallel computing environment based on Windows operating system was constructed and a performance test was mode in comparison with Linux based systems. The Windows 2000 cluster was composed with servers and clients connected by Fast-ethernet, within which two sub-clusters may operates together or separately. Compaq Visual Fortran complier and two MPI libraries, MPICH.NT.1.2.2 and NT-MPICHNT.1.2 were installed as computing tools. Parallel computing performance tests were carried out using two-dimensional preconditioned Navier-Stokes code to examine the dependency on the number of processors, problem size and MPI libraries, those were compared with results from Linux clusters. Results shows that a cluster based on the user-friendly Windows operating system is also useful for the parallel computing and has good performance comparable to the previous Linux clusters.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.30-37
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• 2007

This paper proposes a detection method of position of OFF-switch. Each switch has the parallel path with a serial combination of passive element, its parallel path has each different frequency characteristics. Frequency characteristic of ON-switch reveals a flat spectrum irrelevant to frequency characteristic of passive element connected in parallel to its each terminal and frequency characteristic of OFF-switch reveals the same characteristic as one of passive element connected in parallel. Detection of position of OFF-switch is done by measuring the similarity of each spectrum corresponding to frequency characteristic of passive element connected in parallel to OFF-switch. The measure of their similarity is to calculate Euclidean distance between their test spectrum and reference spectrum. The spectrum with the smallest distance among reference spectrum is recognized as the spectrum of OFF-switch. The real time digital signal processing system is implemented to detect the position of OFF-switch by using spectrum matching.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.26 no.4
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• pp.283-292
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• 2013

The objective of this research is to evaluate of global and local damage for steel-concrete composite structures under highway bridge exposed to fire loading. To enhance the accuracy and efficiency of the numerical analysis, the proposed transient nonlinear thermal structure interaction(TSI) parallel fire analysis method is implemented in ANSYS. To validate the TSI parallel fire analysis method, a comparison is made with the standard fire test results. The proposed TSI parallel fire analysis method is applied to fire damage analysis and performance evaluation for Buchen highway bridge. The result of analysis, temperature of low flange and web are exceed the critical temperature. The deflection and deformation state show good agreement with the fire accident of buchen highway bridge.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.278-284
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• 2009

This paper presents a firing angle controller of a thyristor converter for DC power supply using PID controller with parallel data loop to improve the dynamic response. The proposed parallel data loop for firing angle controller of 3-phase semi-converter, generates pre-measured firing angle according to reference voltage and load current. With the approximated firing angle according to operating conditions, the output voltage can fast keep the reference value with small voltage error. And the PID controller compensates the output voltage error from the firing angle of parallel data loop. In order to reduce the sudden changing of the data from current ripple, a simple digital low pass filter is used to determine the output data. The proposed control scheme is verified by the experimental test of a practical 50[A] grade thyristor converter system.

• Journal of KIISE
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• v.43 no.9
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• pp.1060-1065
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• 2016

Recently, there is an emerging need for parallel UHD video processing, and the usage of computing systems that have an asymmetric processor such as ARM big.LITTLE is actively increasing. Thus, a new parallel UHD video processing method that is optimized for the asymmetric multicore systems is needed. This paper proposes a novel HEVC tile partitioning method for parallel processing by analyzing the computational power of asymmetric multicores. The proposed method analyzes (1) the computing power of asymmetric multicores and (2) the regression model of computational complexity per video resolution. Finally, the model (3) determines the optimal HEVC tile resolution for each core and partitions/allocates the tiles to suitable cores. The proposed method minimizes the gap in the decoding time between the fastest CPU core and the slowest CPU core. Experimental results with the 4K UHD official test sequences show average 20% improvement in the decoding speedup on the ARM asymmetric multicore system.

• Journal of applied mathematics & informatics
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• v.11 no.1_2
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• pp.305-316
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• 2003

Recently, an iterative algorithm for finding the interior eigenvalues of a definite matrix by CG-type method has been proposed. This method compares to the inverse power method. The given matrices A, and B are assumed to be large and sparse, and SPD( Symmetric Positive Definite) The CG scheme for the optimization of the Rayleigh quotient has been proven a very attractive and promising technique for large sparse eigenproblems for smallest eigenvalue. Also, it is very amenable to parallel computations, like the CG method for the linear systems. A proper choice of the preconditioner significantly improves the convergence of the CG scheme. But for parallel computations we need to find an efficient parallel preconditioner. Our candidates we ILU(0) in the wave-front order, ILU(0) in the multi-coloring order, Point-SSOR(Symmetric Successive Overrelaxation), and Multi-Color Block SSOR preconditioner. Wavefront order is a simple way to increase parallelism in the natural order, and Multi-coloring realizes a parallelism of order(N), where N is the order of the matrix. Another choice is the Multi-Color Block SSOR(Symmetric Successive OverRelaxation) preconditioning. Block SSOR is a symmetric preconditioner which is expected to minimize the interprocessor communication due to the blocking. We implemented the results on the CRAY-T3E with 128 nodes. The MPI (Message Passing Interface) library was adopted for the interprocessor communications. The test problem was drawn from the discretizations of partial differential equations by finite difference methods. The results show that for small number of processors Multi-Color ILU(0) has the best performance, while for large number of processors Multi-Color Block SSOR performs the best.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• KIPS Transactions on Software and Data Engineering
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• v.7 no.1
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• pp.25-32
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• 2018

Due to heavy computational cost, deformable object simulation requires more effective collision detection method than rigid body simulation. However, when the CPU-based collision detection algorithm is purely applied to the GPU environment, the collision detection algorithm and the data structure optimized for the GPU environment are essential because the performance of the GPU can not be used properly. Therefore, we propose a GPU-based parallel collision detection algorithm for mass-spring system which is widely used for deformable object representation in this paper. The proposed method uses a parallel algorithm and data structure to reduce collision detection cost through GPU-based curling algorithm using AABB-Octree structure. In this paper, we prove the effectiveness of the proposed method by comparing the intersection test of all triangle pairs in parallel. The results of experimental tests show that the proposed method improves the performance by about 24% on average. Therefore, it is expected that the proposed method can improve the performance of real-time simulation for deformable objects.