• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Journal of the Korean Wood Science and Technology
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• v.49 no.6
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• pp.541-549
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• 2021

This paper reports a method to evaluate the residual strength of insect-damaged radiata pine lumber, such as the screw withdrawal strength as a semi-destructive method and a compression parallel to the grain test to assess the density changes after exposure to outdoor conditions. The screw withdrawal strength test was used as a semi-destructive method to estimate the residual density of decayed lumber. A compression parallel to the grain test was applied to evaluate the residual density. Three variables, such as the screw withdrawal strength, compression parallel to the grain, and residual density, were analyzed statistically to evaluate their relationships. The relationship between the residual density and screw withdrawal strength showed a good correlation, in which the screw withdrawal strength decreased with decreasing density. The other relationship between the residual density and compression parallel to the grain was also positively correlated; the compression parallel to the grain strength decreased with decreasing density. Finally, the correlation between the three variables was statistically significant, and the mutual correlation coefficients showed a strong correlation between the three variables. Hence, these variables are closely correlated. The test results showed that the screw withdrawal strength could be used as a semi-destructive method for an in situ estimation of an existing wood structure. Moreover, the method might approximate the residual density and compression parallel to the grain if supplemented with additional data.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.8
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• pp.475-481
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• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

• Biomaterials and Biomechanics in Bioengineering
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• v.2 no.2
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• pp.111-125
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• 2015

For engineers, generating a mesh in porous media (PMs) sometimes represents a smaller computational load than generating realistic stent geometries with computer fluid dynamics (CFD). For this reason, PMs have recently become attractive to mimic flow-diverter stents (FDs), which are used to treat intracranial aneurysms. PMs function by introducing a hydraulic resistance using Darcy's law; therefore, the pressure drop may be computed by test sections parallel and perpendicular to the main flow direction. However, in previous studies, the pressure drop parallel to the flow may have depended on the width of the gap between the stent and the wall of the test section. Furthermore, the influence of parameters such as the test section geometry and the distance over which the pressure drops was not clear. Given these problems, computing the pressure drop parallel to the flow becomes extremely difficult. The aim of the present study is to resolve this lack of information for stent modeling using PM and to compute the pressure drop using several methods to estimate the influence of the relevant parameters. To determine the pressure drop as a function of distance, an FD was placed parallel and perpendicular to the flow in test sections with rectangular geometries. The inclined angle method was employed to extrapolate the flow patterns in the parallel direction. A similar approach was applied with a cylindrical geometry to estimate loss due to pipe friction. Additionally, the pressure drops were computed by using CFD. To determine if the balance of pressure drops (parallel vs perpendicular) affects flow patterns, we calculated the flow patterns for an ideal aneurysm using PMs with various ratios of parallel pressure drop to perpendicular pressure drop. The results show that pressure drop in the parallel direction depends on test section. The PM thickness and the ratio of parallel permeability to perpendicular permeability affect the flow pattern in an ideal aneurysm. Based on the permeability ratio and the flow patterns, the pressure drop in the parallel direction can be determined.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.364-369
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• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.3
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• pp.209-216
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• 2011

Recently the design of SoCs(System-on-Chips) in which TCM is embedded for high speed operation increases rapidly. In this paper, a parallel test structure for eDRAM-based TCM embedded in SoCs is proposed. In the presented technique, the MUT (Memory Under Test) is changed to parallel structure and it increases testability of MUT with boundary scan chains. The eDRAM is designed in structure for parallel test so that it can be tested for each modules. Dynamic test can be performed based on input-output data. The proposed techniques are verified their performance by circuits simulation.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.42-46
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• 2019

In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• International Journal of Reliability and Applications
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• v.18 no.2
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• pp.45-63
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• 2017

In this paper, we have formulated optimum Accelerated Life Test (ALT) plan for a parallel system with two independent components using masked data with ramp-stress loading scheme and Type-I censoring. Consider a system of two independent and non-identical components connected in parallel. Such a system fails whenever all of its components has failed. The exact component that causes the system to fail is often unknown due to cost and time constraint. For each parallel system at test, we observe its system's failure time and a set of component that includes the component actually causing the system to fail. The stress-life relationship is modelled using inverse power law, and cumulative exposure model is assumed to model the effect of changing stress. The optimal plan consists in finding out the optimum stress rate using D-optimality criterion. The method developed has been explained using a numerical example and sensitivity analysis carried out.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.232-233
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• 2007

In this paper, phenomenon of islanding parallel inverters in an ac-distributed system is proposed. The paper explores the test results of the parallel-connected inverters in grid-connected system. The test results are devised and analyzed taking into account the power quality and the islanding performance. The islanding test methods applied. Experimental results are provided from two 2 kVA inverters connected in parallel, showing the features of islanding test.